參數(shù)資料
型號： PNX8526
廠商： NXP Semiconductors N.V.
英文描述： Programmable source decoder with integrated peripherals
中文描述： 可編程集成外設(shè)源解碼器
文件頁數(shù)： 28/59頁
文件大?。?/td> 3319K
代理商： PNX8526
Philips Semiconductors
PNX8526
Programmable Source Decoder with Integrated Peripherals
Preliminary data
Rev. 01 – 6 October 2003
28 of 59
9397 750 11715
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
TRDY
AD6
PCI
I/O
Parity Error indicates data parity errors during all PCI transactions
except
Special Cycle.
Parity Error indicates data parity errors during all PCI transactions
except
Special Cycle.
Multiplexed Address or Data Bit 15
Multiplexed Address or Data Bit 11
Multiplexed Command or Byte Enable 0
Multiplexed Address or Data Bit 4
Multiplexed Address or Data Bit 1
External I/O Select0
General Purpose Input/Output Bit 5
Audio IN/OUT Data Bit 3
Audio IN/OUT Data Bit 0
ITU-656 VIP Data Bit 8
ITU-656 VIP Data Bit 4
ITU-656 VIP Data Bit 0 (Least Significant Bit)
Audio IN1 OverSample Clock
Audio IN2 OverSample Clock
Digital Video Transport Stream2 Data Bit 5
Digital Video Transport Stream2 Data Bit 2
Digital Video Transport Stream2 Start of Packet
Digital Video Transport Stream2 Data Valid
Digital Video Transport Stream2 Error
System Ground
System Ground
Multiplexed Address or Data Bit 23
Multiplexed Address or Data Bit 21
Multiplexed Address or Data Bit 19
Initiator Ready is asserted during writes to indicate valid data on
AD[31:0]. Also asserted during reads to indicate the target is prepared
to accept data. Wait states are inserted until IRDY and TRDY are both
asserted.
Stop is asserted to indicate a request from the target for the master to
stop the current transmission.
Multiplexed Command or Byte Enable 1
Multiplexed Address or Data Bit 12
Multiplexed Address or Data Bit 8
Multiplexed Address or Data Bit 5
Multiplexed Address or Data Bit 2
XIO Address Bit 25
General Purpose Input/Output Bit 7
PERR
AD7
PCI
I/O
AD[15]
AD[11]
C/BE[0]
AD[04]
AD[01]
XIO_SEL[0]
GPIO[5]
I2S_IO_SD[3]
I2S_IO_SD[0]
DV1_DATA[8]
DV1_DATA[4]
DV1_DATA[0]
I2S_IN1_OSCLK
I2S_IN2_OSCLK
DV2_DATA[5]
DV2_DATA[2]
DV2_SOP
DV2_VALID
DV2_ERR
V
SS
V
SS
AD[23]
AD[21]
AD[19]
IRDY
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AE1
AE2
AE3
AE4
AE5
AE6
PCI
PCI
PCI
PCI
PCI
MISC
GPIO
AVIF
AVIF
DVB
DVB
DVB
AVIF
AVIF
DVB
DVB
DVB
DVB
DVB
PWR
PWR
PCI
PCI
PCI
PCI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
I
I
I
I
I
-
-
I/O
I/O
I/O
I/O
STOP
AE7
PCI
I/O
C/BE[1]
AD[12]
AD[08]
AD[05]
AD[02]
XIO_A25
GPIO[7]
AE8
AE9
AE10
AE11
AE12
AE13
AE14
PCI
PCI
PCI
PCI
PCI
MISC
GPIO
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Table 16:
Symbol
All pins
…continued
Pin
Group
Type
Description
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