參數(shù)資料
型號： PNX8526
廠商： NXP Semiconductors N.V.
英文描述： Programmable source decoder with integrated peripherals
中文描述： 可編程集成外設(shè)源解碼器
文件頁數(shù)： 30/59頁
文件大?。?/td> 3319K
代理商： PNX8526
Philips Semiconductors
PNX8526
Programmable Source Decoder with Integrated Peripherals
Preliminary data
Rev. 01 – 6 October 2003
30 of 59
9397 750 11715
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
6.2.1
Multi-function pins
Table 17
identifies and describes alternate signals that are available in the PNX8526.
In
Section 6.2
alternate signals are also identified by a hash (#) within each functional
group of signals.
Remark:
The PNX8526 has a number of General Purpose Input Output (GPIO) pins.
Some of these are dedicated pins, while others are configured as alternate signals on
multi function pins, as described below. The standard function of these pins may not
be required in some system configurations.
For more details on GPIO functionality, see
PNX8526 User Manual, Chapter 10
.
DV2_DATA[0]
V
SS
V
SS
AF24
AF25
AF26
DVB
PWR
PWR
I
-
-
Digital Video Transport Stream2 Data Bit 0
System Ground
System Ground
Table 16:
Symbol
All pins
…continued
Pin
Group
Type
Description
Table 17:
In this table,”Type” reflects mux pin function only. A pin may have other “Type” capabilities as noted in its functional group. See
Section 6.2
for more details.
Pin
MUX contacts Primary
signal and Alternate
Function
AF15
I2S_IO_OSCLK
I/O
Audio IN/OUT Oversample Clock
GPIO 45
I/O
General Purpose Input/Output 45
AE15
I2S_IO_SCK
I/O
Audio IN/OUT Serial Clock
GPIO 46
I/O
General Purpose Input/Output 46
AC15
I2S_IO_WS
I/O
Audio IN/OUT Word Select
GPIO 47
I/O
General Purpose Input/Output 47
AD15
I2S_IO_SD[3]
I/O
Audio IN/OUT Data Bit 3
GPIO 51
I/O
General Purpose Input/Output 51
AF16
I2S_IO_SD[2]
I/O
Audio IN/OUT Data Bit 2
GPIO 50
I/O
General Purpose Input/Output 50
AE16
I2S_IO_SD[1]
I/O
Audio IN/OUT Data Bit 1
GPIO 49
I/O
General Purpose Input/Output 49
AD16
I2S_IO_SD[0]
I/O
Audio IN/OUT Data Bit 0
GPIO 48
I/O
General Purpose Input/Output 48
R1
DV_CLK2
O
Digital Video Clock2 for secondary display channel from AICP
R2
DV_OUT2[9]
O
Digital Video Output2, Bit 9 for secondary display channel from AICP
SPY_OUT[9]
O
SPY Micro-Architecture Output signal, Bit 9
R4
DV_OUT2[8]
O
Digital Video Output2, Bit 8 for secondary display channel from AICP
SPY_OUT[8]
O
SPY Micro-Architecture Output signal, Bit 8
DSU_TPC1
O
Debug Support Unit1, TPC1
R3
DV_OUT2[7]
O
Digital Video Output2, Bit 7 for secondary display channel from AICP
SPY_OUT[7]
O
SPY Micro-Architecture Output signal, Bit 7
DSU_TPC0
O
Debug Support Unit0, TPC0
Multiplexed (MUX) pins
Type
Description
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