參數(shù)資料
型號(hào)： PNX8526
廠商： NXP Semiconductors N.V.
英文描述： Programmable source decoder with integrated peripherals
中文描述： 可編程集成外設(shè)源解碼器
文件頁數(shù)： 51/59頁
文件大?。?/td> 3319K
代理商： PNX8526
Philips Semiconductors
PNX8526
Programmable Source Decoder with Integrated Peripherals
Preliminary data
Rev. 01 – 6 October 2003
51 of 59
9397 750 11715
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
13.14 JTAG test contacts
14. Delta compared to PNX8525
There are a number of differences between the PNX8526 and the PNX8525 with
respect to the physical interfacing of the device. These differences are described in
Table 38
.
Fig 19. JTAG timing
Table 37:
Symbol
t
clk(TDO)
t
su(TCK)
t
h(TCK)
JTAG timing
Parameter
JTAG_TCK to JTAG_TDO Valid delay
Input Setup Time JTAG_TCK
Input Setup Time JTAG_TCK
Min
TBD
TBD
TBD
Max
Unit
handbook, 4 columns
valid
TDI
TMS
TCK
TDO
valid
MCE557
tsu(TCK)
tclk(TDO)
th(TCK)
Table 38:
Characteristic
Core supply voltage
Differences - 8525 / 8526
PNX8525
PNX8526
1.8 V ± 5%
1.26 V ± 0.06 V
I2C-bus pads
GPIO pads with schmitt trigger and pull-ups
Special I
2
C pads designed to meet the I
2
C
specification
IEEE-1394 pads
GPIO pads with schmitt trigger and pull-ups
Special IEEE-1394 pads designed to meet the
IEEE-1394 Link to Phy specification
PCI Interface
Supports 5 V tolerant interface with 3.3 V
signalling
No 5 V tolerant interface, all signals limited to 3.3 V
System reset output (SYS_RSTN_OUT)
Drive capability 12 mA
Drive capability 8 mA
Clock output (PLL_OUT)
Drive capability 12 mA
Drive capability 8 mA
SPDIF output
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