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參數(shù)資料
| 型號(hào)： | PNX8526 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Programmable source decoder with integrated peripherals |
| 中文描述： | 可編程集成外設(shè)源解碼器 |
| 文件頁數(shù)： | 11/59頁 |
| 文件大?。?/td> | 3319K |
| 代理商： | PNX8526 |
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Philips Semiconductors
PNX8526
Programmable Source Decoder with Integrated Peripherals
Preliminary data
Rev. 01 – 6 October 2003
11 of 59
9397 750 11715
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Table 9:
Symbol
PHY_D[7]
PHY_D[6]
PHY_D[5]
PHY_D[4]
PHY_D[3]
PHY_D[2]
PHY_D[1]
PHY_D[0]
PHY_CTL[1]
PHY_CTL[0]
PHY_LREQ
IEEE 1394 port
Pin
B9
D10
C9
A8
B8
D9
C8
A7
B7
C7
B5
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
Description
PHY Data Bit 7. Data is expected on pins 7:0 for 400 MB packets.
PHY Data Bit 6. Data is expected on pins 7:0 for 400 MB packets.
PHY Data Bit 5. Data is expected on pins 7:0 for 400 MB packets.
PHY Data Bit 4. Data is expected on pins 7:0 for 400 MB packets.
PHY Data Bit 3. Data is expected on pins 3:0 for 200 MB packets.
PHY Data Bit 2. Data is expected on pins 3:0 for 200 MB packets.
PHY Data Bit 1. Data is expected on pins 1:0 for 100 MB packets.
PHY Data Bit 0. Data is expected on pins 1:0 for 100 MB packets.
PHY Control Bit 1. Indicates the mode for data on the Din port.
PHY Control Bit 0. Indicates the mode for data on the Din port.
Used by the link to make bus requests and to access PHY registers. This is a serial
bus. A train of pulses is sent on this signal.
Signals which type of isolation mode is used at the PHY-Link interface.
0 = This is 1394-1995 Annex J type isolation. Enables differentiator circuitry.
1 = Direct connection or single capacitor isolation mode. This will disable the
differentiator circuitry.
System clock. 49.152 MHz input
PHY_ISO_N
A6
I
CLK_L1394
D8
I
Table 10:
Symbol
I2C1_SCL
I2C1_SDA
I2C2_SCL
I2C2_SDA
Serial communication port (I
2
C)
Pin
Type
D6
I/O
A4
I/O
H1
I/O
K4
I/O
Description
Serial Communications Port (I
2
C-bus) Clock
Serial Communications Port (I
2
C-bus) Data
Serial Communications Port (I
2
C-bus) Clock
Serial Communications Port (I
2
C-bus) Data
Table 11:
# indicates multiplexed signal, see
Section 6.2.1
for more details.
Symbol
Pin
Type Description
Audio and video interface
Alternate
Function
DV_OUT1[9]
DV_OUT1[8]
DV_OUT1[7]
DV_OUT1[6]
DV_OUT1[5]
DV_OUT1[4]
DV_OUT1[3]
DV_OUT1[2]
DV_OUT1[1]
DV_OUT1[0]
DV_OUT2[9]
DV_OUT2[8]
DV_OUT2[7]
M2
M1
N4
N3
N1
N2
P2
P1
P4
P3
R2
R4
R3
O
O
O
O
O
O
O
O
O
O
O
O
O
Digital Video Output1, Bit 9 for primary display channel from AICP
Digital Video Output1, Bit 8 for primary display channel from AICP
Digital Video Output1, Bit 7 for primary display channel from AICP
Digital Video Output1, Bit 6 for primary display channel from AICP
Digital Video Output1, Bit 5 for primary display channel from AICP
Digital Video Output1, Bit 4 for primary display channel from AICP
Digital Video Output1, Bit 3 for primary display channel from AICP
Digital Video Output1, Bit 2 for primary display channel from AICP
Digital Video Output1, Bit 1 for primary display channel from AICP
Digital Video Output1, Bit 0 for primary display channel from AICP
Digital Video Output2, Bit 9 for secondary display channel from AICP
Digital Video Output2, Bit 8 for secondary display channel from AICP
Digital Video Output2, Bit 7 for secondary display channel from AICP
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