參數(shù)資料
型號： PNX8526
廠商： NXP Semiconductors N.V.
英文描述： Programmable source decoder with integrated peripherals
中文描述： 可編程集成外設(shè)源解碼器
文件頁數(shù)： 29/59頁
文件大小： 3319K
代理商： PNX8526
Philips Semiconductors
PNX8526
Programmable Source Decoder with Integrated Peripherals
Preliminary data
Rev. 01 – 6 October 2003
29 of 59
9397 750 11715
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
I2S_IO_SCK
I2S_IO_SD[1]
DV1_DATA[9]
DV1_DATA[5]
DV1_DATA[2]
DV1_CLK
I2S_IN1_SD
I2S_IN2_SD
DV2_DATA[4]
DV2_DATA[1]
V
SS
V
SS
V
SS
V
SS
IDSEL
AE15
AE16
AE17
AE18
AE19
AE20
AE21
AE22
AE23
AE24
AE25
AE26
AF1
AF2
AF3
AVIF
AVIF
DVB
DVB
DVB
DVB
AVIF
AVIF
DVB
DVB
PWR
PWR
PWR
PWR
PCI
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
I
-
-
-
-
I/O
Audio IN/OUT Serial Clock
Audio IN/OUT Data Bit 1
ITU-656 VIP Data Bit 9 (Most Significant Bit)
ITU-656 VIP Data Bit 5
ITU-656 VIP Data Bit 2
ITU-656 VIP Data Clock
Audio IN1 Data
Audio IN2 Data
Digital Video Transport Stream2 Data Bit 4
Digital Video Transport Stream2 Data Bit 1
System Ground
System Ground
System Ground
System Ground
Initialization Device Select provides chip select during configuration
read and write transactions.
Multiplexed Address or Data Bit 22
Multiplexed Command or Byte Enable 2
Frame is asserted to indicate start of bus transaction and remains
asserted until final data phase begins.
Device Select is asserted when a target address is decoded and
remains asserted to indicate that a target device is selected.
Parity supports even parity across the PCI Address/Data Bus
AD[31:0]) and Command/ Byte Enable Bus (C/BE[3:0]). Bus Master
drives PAR for address and write data phases. Target drives PAR for
the read data phases.
Multiplexed Address or Data Bit 13
Multiplexed Address or Data Bit 9
Multiplexed Address or Data Bit 6
External I/O Select2
XIO Acknowledge (EEPROM)
General Purpose Input/Output Bit 6
Audio IN/OUT OverSample Clock
Audio IN/OUT Data Bit 2
Multi-ch/SPDIF Input
ITU-656 VIP Data Bit 7
ITU-656 VIP Data Bit 3
ITU-656 VIP Data Valid
Audio IN1 Word Select
Audio IN2 Word Select
Digital Video Transport Stream2 Data Bit 7
AD[22]
C/BE[2]
FRAME
AF4
AF5
AF6
PCI
PCI
PCI
I/O
I/O
I/O
DEVSEL
AF7
PCI
I/O
PAR
AF8
PCI
I/O
AD[13]
AD[09]
AD[06]
XIO_SEL[2]
XIO_ACK
GPIO[6]
I2S_IO_OSCLK
I2S_IO_SD[2]
SPDIF_IN
DV1_DATA[7]
DV1_DATA[3]
DV1_VALID
I2S_IN1_WS
I2S_IN2_WS
DV2_DATA[7]
AF9
AF10
AF11
AF12
AF13
AF14
AF15
AF16
AF17
AF18
AF19
AF20
AF21
AF22
AF23
PCI
PCI
PCI
MISC
MISC
GPIO
AVIF
AVIF
AVIF
DVB
DVB
DVB
AVIF
AVIF
DVB
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I/O
I/O
I/O
I/O
I/O
I
Table 16:
Symbol
All pins
…continued
Pin
Group
Type
Description
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