PNX1300/01/02/11 Data Book
Philips Semiconductors
3-6
PRELIMINARY SPECIFICATION
3.2.3
Compute Operations
Compute operations are register-to-register operations.
The specified operation is performed on one or two
source registers and the result is written to the destina-
tion register.
Immediate Operations.
Immediate operations load an
immediate constant (specified in the opcode) and pro-
duce a result in the destination register.
Floating-Point Compute Operations.
Floating-point
compute operations are register-to-register operations.
The specified operation is performed on one or two
source registers and the result is written to the destina-
tion register. Unless otherwise mentioned all floating
point operations observe the rounding mode bits defined
in the PCSW register. All floating-point operations not
ending in
‘
flags
’
update the PCSW exception flags. All
operations ending in
‘
flags
’
compute the exception flags
as if the operation were executed and return the flag val-
ues (in the same format as in the PCSW); the exception
flags in the PCSW itself remain unchanged.
Multimedia Operations.
These special compute opera-
tions are like normal compute operations, but the speci-
fied operations are not usually found in general purpose
CPUs. These operations provide special support for mul-
timedia applications.
3.2.4
Special-Register Operations
Special register operations operate on the special regis-
ters: PCSW, DPC, SPC and CCCOUNT.
3.2.5
Control-Flow Operations
Control-flow operations change the value of the program
counter. Conditional jumps test the value in a register
and, based on this value, change the program counter to
the address contained in a second register or continue
execution with the next instruction. Unconditional jumps
always change the program counter to the specified im-
mediate address.
Control-flow operations can be interruptible or non-inter-
ruptible. Execution of an interruptible jump is the only oc-
casion where PNX1300 allows special event handling to
take place (see
Section 3.5,
“
Special Event Handling
”
).
3.3
PNX1300 INSTRUCTION ISSUE RULES
The PNX1300 VLIW CPU allows issue of 5 operations in
each clock cycle according to a set of specific issue
rules. The issue rules impose issue time constraints and
a result writeback constraint. Any set of operations that
meets all constraints constitutes a legal PNX1300 in-
struction. A more extensive description and a few special
case issue rules and limitations can be found in the Phil-
ips TriMedia SDE documentation.
Issue time constraints:
an operation implies a need for a functional unit type
(as documented in
Appendix A,
“
PNX1300/01/02/11
DSPCPU Operations.
”
)
each operation requires an issue slot that has an
instance of the appropriate functional unit type
attached
FALU
DSPMUL
DSPMUL
FALU
DMEMSPEC
SHIFTER
SHIFTER
FCOMP
DMEM
DMEM
BRANCH
BRANCH
BRANCH
IFMUL
IFMUL
DSPALU
FTOUGH
(latency 17,
recovery 16)
DSPALU
ALU
ALU
ALU
ALU
ALU
CONST
CONST
CONST
CONST
CONST
issue slot 1
issue slot 2
issue slot 3
issue slot 4
issue slot 5
Figure 3-3. PNX1300 issue slots, functional units, and latency.