
PNX1300/01/02/11 Data Book
Philips Semiconductors
8-4
PRELIMINARY SPECIFICATION
In MSB-first mode, the serial-to-parallel converter as-
signs the value of the bit at LEFTPOS to LEFT[15]. Sub-
sequent bits are assigned, in order, to decreasing bit po-
sitions in the LEFT data word, up to and including
LEFT[SSPOS]. Bits LEFT[SSPOS
–
1:0] are cleared.
Hence, in MSB-first mode, an arbitrary number of bits are
captured. They are left-adjusted in the 16-bit parallel out-
put of the converter.
In LSB-first mode, the serial to parallel converter assigns
the value of the bit at LEFTPOS to LEFT[SSPOS]. Sub-
sequent bits are assigned, in order, to increasing bit po-
sitions in the LEFT data word, up to and including
LEFT[15]. Bits LEFT[SSPOS
–
1:0] are cleared. Hence, in
LSB-first mode, an arbitrary number of bits are captured.
They are returned left-adjusted in the 16-bit parallel out-
put of the converter.
Refer to
Figure 8-3
and
Table 8-6
to see an example of
how the AI unit MMIO registers are set to collect 16-bit
samples using the Philips SAA7366 I
2
S 18-bit A/D con-
verter. This setup assumes the SAA7366 acts as the se-
rial master.
For example, if it were desirable to use only the 12 MSBs
of the A/D converter in
Figure 8-3
, use the settings of
Table 8-6
with SSPOS set to
‘
4
’
. This results in
LEFT[15:4] being set with data bits 0..11, and LEFT[3:0]
being set to
’
0
’
. RIGHT[15:4] is set with data bits 32..43
and RIGHT[3:0] is set to
’
0
’
.
8.6
MEMORY DATA FORMATS
The AI unit autonomously writes samples to memory in
mono and stereo 8- and 16-bits per sample formats, as
shown in
Figure 8-4
. Successive samples are always
stored at increasing memory address locations. The set-
ting of the LITTLE_ENDIAN bit in the AI_CTL register de-
CLOCK_EDGE
if
‘
0
’
(RESET default) the AI_SD and AI_WS
pins are sampled on positive edges of the
AI_SCK pin. If SER_MASTER =1, AI_WS is
asserted on negative edges of AI_SCK.
if 1, AI_SD and AI_WS are sampled on neg-
ative edges of AI_SCK. As output, AI_WS
is asserted on positive edges of AI_SCK.
Table 8-5. AI MMIO serial framing control fields
Field Name
Description
Figure 8-3. Serial frame of the SAA7366 18 bit I
2
S A/D converter (format 2 SWS).
1
63
62
52
51
50
34
33
32
31
19
18
AI_SCK
AI_WS
AI_SD
left
n
(18)
3
2
1
0
right
n
(18)
0
left
n+1
(18)
Table 8-6. Example setup for SAA7366
Field
Value
Explanation
SER_MASTER
FREQUENCY
0
SAA7366 is serial master
256f
s
44.1 kHz
AI_SCK set to AI_OSCLK/4
(not needed since
SER_MASTER=0)
Serial frame length of 64 bits
(not needed since
SER_MASTER=0)
Frame starts with neg. AI_WS
Take a sample each ser. frame
Don
’
t care
Bit position 0 is MSB of left
channel and will go to
LEFT[15]
Bit position 32 is MSB of right
channel and will go to
RIGHT[15]
MSB first
Stop with LEFT/RIGHT[0]
Sample WS and SD on posi-
tive SCK edges for I
2
S
161628209
SCKDIV
3
WSDIV
63
POLARITY
FRAMEMODE
VALIDPOS
LEFTPOS
0
00
n/a
0
RIGHTPOS
32
DATAMODE
SSPOS
CLOCK_EDGE
0
0
0
Figure 8-4. AI memory DMA formats.
adr
left
n
adr+1
left
n+1
adr+2
left
n+2
adr+3
left
n+3
adr+4
left
n+4
adr+5
left
n+5
adr+6
left
n+6
adr+7
left
n+7
8-bit
mono
adr
left
n
adr+1
right
n
adr+2
left
n+1
adr+3
right
n+1
adr+4
left
n+2
adr+5
right
n+2
adr+6
left
n+3
adr+7
right
n+3
8-bit
stereo
16-bit
mono
left
n
adr
left
n+1
adr+2
left
n+2
adr+4
left
n+3
adr+6
16-bit
stereo
left
n
adr
right
n
adr+2
left
n+1
adr+4
right
n+1
adr+6