PNX1300/01/02/11 Data Book
Philips Semiconductors
18-4
PRELIMINARY SPECIFICATION
TriMedia JTAG controller. The interface module may
be a PC plug-in board.
This module may transfer data from and to the host
computer in bit-serial or word-parallel fashion. It
transfers data from and to the JTAG registers on a
TriMedia processor in bit-serial fashion in accordance
with the IEEE 1149.1 standard. The JTAG interface
module connects to a 4-pin JTAG connector on a Tri-
Media board which provides a path to the JTAG pins
on a TriMedia processor. It is the responsibility of the
interface module to scan data in and out of the TriMe-
dia processor into its internal buffers and make them
available to the host computer.
A JTAG controller on the TriMedia processor
which provides a bridge between the external
JTAG TAP and the internal system.
The controller transfers data from/to the TAP to/from
its scannable registers asynchronous to the internal
system clock. A monitor running on a TriMedia pro-
cessor and the debugger front-end running on a host
computer exchange data via JTAG by reading/writing
the MMIO registers reserved for this purpose, includ-
ing a control register used for the handshake.
18.3.1
JTAG Instruction and Data Registers
.
PNX1300 has two JTAG data registers and one JTAG
control register (see
Figure 18-3
) in MMIO space and a
number a JTAG instructions to manipulate those regis-
ters.
Table 18-2
lists the MMIO addresses of the JTAG
data and control registers. The addresses are offsets
from MMIO_BASE. All references to instruction and data
registers below are JTAG instructions and data registers
and not TriMedia instruction or data registers.
Two 32-bit data registers, JTAG_DATA_IN and
JTAG_DATA_OUT in MMIO space.
Both registers
can be connected in between TDI and TDO like the
standard Bypass and Boundary Scan registers of
JTAG (not shown in
Figure 18-3
).
The JTAG_DATA_IN register can be read or written to
via the JTAG port. The JTAG_DATA_OUT register is
read-only via the JTAG port, so that scanning out
JTAG_DATA_OUT is non-destructive.
The JTAG_DATA_IN and JTAG_DATA_OUT are read-
able/writable from the TriMedia processor via the
usual load/store operations.
An 8-bit control register JTAG_CTRL in MMIO
space.
The JTAG_CTRL register is used for hand-
shake between a debug monitor running on a TriMe-
dia and a debugger front-end running on a host.
JTAG_CTRL.ofull =
‘
1
’
means that JTAG_DATA_OUT
has valid data to be scanned out. On power-on reset
of the TriMedia processor, JTAG_CTRL.ofull =
‘
0
’
.
JTAG_CTRL.ofull is both readable and writable via
JTAG tap. Writing 0 to JTAG_CTRL.ofull via JTAG is a
‘
remember
’
operation, i.e., JTAG_CTRL.ofull retains
its previous state. Writing a
‘
1
’
to JTAG_CTRL.ofull
via JTAG is a
‘
clear
’
operation, i.e., JTAG_CTRL.ofull
becomes
‘
0
’
.
JTAG_CTRL.ifull =
‘
0
’
means that the JTAG_DATA_IN
register is empty. JTAG_CTRL.ifull = 1 means that
JTAG_DATA_IN has valid data and the debug monitor
has not yet copied it to its private area. On power-on
reset of the TriMedia processor, JTAG_CTRL.ifull = 0.
JTAG_CTRL.ifull is readable and writable via JTAG.
Writing a
‘
0
’
to JTAG_CTRL.ifull via JTAG is a
remember operation, i.e., JTAG_CTRL.ifull retains it
previous state. Writing a
‘
1
’
to JTAG_CTRL.ifull posts
an interrupt on hardware line 18.
The peripheral blocks on a TriMedia processor may
enter a
‘
power down
’
state to reduce power con-
sumption. The JTAG_CTRL.sleepless bit determines
if the JTAG block participates in a power down state.
In the power-on RESET state, JTAG_CTRL.sleepless
bit is
‘
1
’
meaning the JTAG block does not power
down. It can be read and written to by the TriMedia
processor via load/store operations and by the
debugger front-end running on a host by scan in/out.
Two
virtual
registers,
JTAG_OFULL_OUT.
The
JTAG_IFULL_IN
connects
JTAG_IFULL_IN
first
virtual
the
and
register
registers
Table 18-2. MMIO Register Assignments
MMIO Offset
JTAG Register
0x 10 3800
0x 10 3804
0x 10 3808
JTAG_DATA_IN
JTAG_DATA_OUT
JTAG_CTRL
To
TDO
JTAG_DATA_IN
JTAG_DATA_OUT
JTAG_CTRL
from
TDI
0
1
ifull
ofull
unused bits
7
0
31
31
0
Figure 18-3. Additional JTAG data registers and control register
2
sleepless
bit
3