- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄383727 > OX16PCI952 (Electronic Theatre Controls, Inc.) Integrated High Performance Dual UARTs, Parallel Port and 5.0v PCI interface PDF資料下載
參數(shù)資料
| 型號： | OX16PCI952 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Integrated High Performance Dual UARTs, Parallel Port and 5.0v PCI interface |
| 中文描述： | 集成高性能的雙UART，并行端口和5.0V PCI接口 |
| 文件頁數(shù)： | 59/76頁 |
| 文件大小： | 1386K |
| 代理商： | OX16PCI952 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁當(dāng)前第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁
9.1.3
Zone2 of the EEPROMallows the end-user to override the
default settings of the Local Configuration Registers to
meet their specific applications. Accesses require one or
more configuration WORDs. Registers are selected using a
7-bit byte-offset field. This offset value is the offset from
Base Address Registers in I/O or memory space (see
section 6.4).
Note: Not all of the registers in the Local
Configuration Register set are writable by the EEPROM.
(See section “Accessing the Local Configuration
Registers”).
The format of configuration WORDs for the Local
Configuration Registers in Zone 2 are described in the
following table.
Bits Description
15
‘0’ = There are no more Configuration WORDs
to follow in Zone2. Move to the next available
zone or end EEPROMprogramif no more zones
are enabled in the Header.
‘1’ = There is another Configuration WORD to
follow for the Local Configuration Registers.
14:8 These seven bits define the byte-offset of the
Local configuration register to be programmed.
For example the byte-offset for LCC[23:16] is
0x02.
7:0
8-bit value of the register to be programmed
EEPROM Word Format for Zone 2
9.1.4
Zone 3 : Identification Registers
Zone 3 of the EEPROMallows the end-user to change the
Vendor and/or SubsystemVendor ID’s of both logical
functions, to suit their requirements. Writes to this zone
affects the corresponding fields in the PCI Configuration
Space of both function 0 and function 1.
The format of Device Identification configuration WORDs
are described in Table 27.
Bits
Description
15
‘0’ = There are no more Zone 3 (Identification)
bytes to program Move to the next available
zone or end EEPROM programif no more zones
are enabled in the Header.
‘1’ = There is another Zone 3 (Identification) byte
to follow.
DataSheet Revision 1.1
Page 59
OX16PCI952
OXFORD SEMICONDUCTOR LTD.
Zone2: Local Configuration Register Zone
14:8
0x00 = Vendor ID bits [7:0].
0x01 = Vendor ID bits [15:8].
0x02 = SubsystemVendor ID [7:0].
0x03 = SubsystemVendor ID [15:8].
0x03 to 0x7F = Reserved.
8-bit value of the register to be programmed
7:0
Table 27: Zone 3 data format
9.1.5
Zone 4 of the EEPROMallows the end-user to alter the
default values/settings of the PCI Configuration Space
registers of both functions, independently. This excludes
writes to the Vendor ID and SubsystemVendor ID fields
that can be written only through Zone 3).
This zone is divided into two groups, one for the PCI
Configuration Space of function 0 and one for function 1.
Each group consists of a function header WORD, and one
or more configuration WORDs for that function.
The function header is described in the following table.
Bits
Description
15
‘0’ = End of Zone 4.
‘1’ = Define this function header.
14:3
Reserved. Write zeros.
2:0
Function number for the following configuration
WORD(s).
‘000’ = Function 0 (UARTs)
‘001’ = Function 1 (Parallel Port)
Other values = Reserved.
The subsequent WORDs for each function contain the
address offset and a byte of programmng data for the PCI
Configuration Space belonging to the function number
selected by the proceeding Function-Header. The format of
configuration WORDs for the PCI Configuration Registers
are described below.
Bits
Description
15
‘0’ = This is the last configuration WORD in for
the selected function in the Function-Header.
‘1’ = There is another WORD to follow for this
function.
14:8
These seven bits define the byte-offset of the PCI
configuration register to be programmed. For
example the byte-offset of the Interrupt Pin
register is 0x3D. Offset values are tabulated in
section 6.2.
7:0
8-bit value of the register to be programmed
Zone 4 : PCI Configuration Registers
Table 28: Zone 4 data format (data)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| OX16PCI952-TQFP-A | Integrated High Performance Dual UARTs, Parallel Port and 5.0v PCI interface |
| OX16PCI954 | Integrated Quad UART and PCI interface |
| OX16PCI954-TQC60-A | Integrated Quad UART and PCI interface |
| OX4240 | OCXO |
| OX1040 | OCXO |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| OX16PCI952_05 | 制造商:OXFORD 制造商全稱:OXFORD 功能描述:Integrated High Performance Dual UARTs, Parallel Port and 5.0v PCI interface |
| OX16PCI952-TQAG | 制造商:PLX Technology 功能描述: 制造商:Oxford Semiconductor 功能描述:IC PCI BRIDGE DUAL PORT UART SMD |
| OX16PCI952-TQC60-A | 制造商:OXFORD 制造商全稱:OXFORD 功能描述:Integrated High Performance Dual UARTs, Parallel Port and 5.0v PCI interface |
| OX16PCI952-TQFP-A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Integrated High Performance Dual UARTs, Parallel Port and 5.0v PCI interface |
| OX16PCI954 | 制造商:OXFORD 制造商全稱:OXFORD 功能描述:Integrated Quad UART and PCI interface |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。