參數(shù)資料
型號(hào)： OX16PCI952
廠商： Electronic Theatre Controls, Inc.
英文描述： Integrated High Performance Dual UARTs, Parallel Port and 5.0v PCI interface
中文描述： 集成高性能的雙UART，并行端口和5.0V PCI接口
文件頁(yè)數(shù)： 35/76頁(yè)
文件大?。?/td> 1386K
代理商： OX16PCI952
DataSheet Revision 1.1
Page 35
OX16PCI952
OXFORD SEMICONDUCTOR LTD.
7.4
Transmitter and receiver FIFOs
Both the transmtter and receiver have associated holding
registers (FIFOs), referred to as the transmtter holding
register (THR) and receiver holding register (RHR)
respectively.
In normal operation, when the transmtter finishes
transmtting a byte it will remove the next data fromthe top
of the THR and proceed to transmt it. If the THR is empty,
it will wait until data is written into it. If THR is empty and
the last character being transmtted has been completed
(i.e. the transmtter shift register is empty) the transmtter is
said to be idle. Simlarly, when the receiver finishes
receiving a byte, it will transfer it to the bottomof the RHR.
If the RHR is full, an overrun condition will occur (see
section 7.5.3).
Data is written into the bottomof the THR queue and read
fromthe top of the RHR queue completely asynchronously
to the operation of the transmtter and receiver.
The size of the FIFOs is dependent on the setting of the
FCR register. When in Byte mode, these FIFOs only
accept one byte at a time before indicating that they are
full; this is compatible with the 16C450. When in a FIFO
mode, the size of the FIFOs is either 16 (compatible with
the 16C550) or 128.
Data written to the THR when it is full is lost. Data read
fromthe RHR when it is empty is invalid. The empty or full
status of the FIFOs are indicated in the Line Status
Register ‘LSR’ (see section 7.5.3). Interrupts are generated
when the UART is ready for data transfer to/fromthe
FIFOs. The number of items in each FIFO may also be
read back fromthe transmtter FIFO level (TFL) and
receiver FIFO level (RFL) registers (see section 7.11.2).
7.4.1
FIFO Control Register ‘FCR’
FIFO setup:
FCR[0]: Enable FIFO mode
logic 0
Byte mode.
logic 1
FIFO mode.
This bit should be enabled before setting the FIFO trigger
levels.
FCR[1]: Flush RHR
logic 0
No change.
logic 1
Flushes the contents of the RHR
This is only operative when already in a FIFO mode. The
RHR is automatically flushed whenever changing between
Byte mode and a FIFO mode. This bit will return to zero
after clearing the FIFOs.
FCR[2]: Flush THR
logic 0
No change.
logic 1
Flushes the contents of the THR, in the same
manner as FCR[1] does for the RHR.
THR Trigger levels:
FCR[3]: Tx trigger level enable
logic 0
Transmt trigger levels enabled
logic 1
Transmt trigger levels disabled
When FCR[3]=0, the transmtter trigger level is always set
to 1, thus ignoring FCR[5:4]. Alternatively, 950-mode
trigger levels can be set using ACR[5].
FCR[5:4]: Compatible trigger levels
450, 550 and extended 550 modes:
The transmtter interrupt trigger levels are set to 1 and
FCR[5:4] are ignored.
650 mode:
In 650 mode the transmtter interrupt trigger levels can be
set to the following values:
FCR[5:4]
Transmit Interrupt Trigger level
00
01
10
11
16
32
64
112
Table 14: Transmit Interrupt Trigger Levels
These levels only apply when in Enhanced mode and when
FCR[3] is set, otherwise the trigger level is set to 1. A
transmtter empty interrupt will be generated (if enabled) if
the TFL falls below the trigger level.
750 Mode:
In 750 compatible mode, transmtter trigger level is set to 1,
FCR[4] is unused and FCR[5] defines the FIFO depth as
follows:
FCR[5]=0: FIFO size is 16 bytes.
FCR[5]=1: FIFO size is 128 bytes.
In non-Enhanced mode and when FIFOSEL pin is low,
FCR[5] is writable only when LCR[7] is set. Note that in
Enhanced mode, the FIFO size is increased to 128 bytes
when FCR[0] is set.
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