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參數(shù)資料
| 型號(hào)： | OX16PCI952 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Integrated High Performance Dual UARTs, Parallel Port and 5.0v PCI interface |
| 中文描述： | 集成高性能的雙UART，并行端口和5.0V PCI接口 |
| 文件頁數(shù)： | 48/76頁 |
| 文件大?。?/td> | 1386K |
| 代理商： | OX16PCI952 |
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ACR[5]: 950 mode trigger levels enable
logic 0
Interrupts and flow control trigger levels are as
described in FCR register and are compatible
with 16C650/16C750 modes.
logic 1
950 specific enhanced interrupt and flow
control trigger levels defined by RTL, TTL, FCL
and FCH are enabled.
ACR[6]: ICR read enable
logic 0
The Line Status Register is readable.
logic 1
The Indexed Control Registers are readable.
Setting this bit will map the ICR set to the LSR location for
reads. During normal operation this bit should be cleared.
ACR[7]: Additional status enable
logic 0
Access to the ASR, TFL and RFL registers is
disabled.
logic 1
Access to the ASR, TFL and RFL registers is
enabled.
When ACR[7] is set, the MCR, LCR and IER registers are
no longer readable but remain writable, and the registers
ASR, TFL and RFL replace themin the register map for
read operations. The software driver may leave this bit set
during normal operation, since MCR, LCR and IER do not
generally need to be read.
7.11.4 Transmitter Trigger Level ‘TTL’
The TTL register is located at offset 0x04 of the ICR
Whenever 950 trigger levels are enabled (ACR[5]=1), bits 4
and 5 of FCR are ignored and an alternative arbitrary
transmtter interrupt trigger level can be defined in the TTL
register. This 7bit value provides a fully programmable
transmtter interrupt trigger facility. In 950 mode, a priority
level 3 interrupt occurs indicating that the transmtter buffer
requires more characters when the interrupt is not masked
(IER[1]=1) and the transmtter FIFO level falls below the
value stored in the TTL register. The value 0 (0x00) has a
special meaning. In 950 mode when the user writes 0x00
to the TTL register, a level 3 interrupt only occurs when the
FIFO and the transmtter shift register are both empty and
the SOUT line is in the idle marking state. This feature is
particularly useful to report back the empty state of the
transmtter after its FIFO has been flushed away.
7.11.5 Receiver Interrupt. Trigger Level ‘RTL’
The RTL register is located at offset 0x05 of the ICR
Whenever 950 trigger levels are enabled (ACR[5]=1), bits 6
and 7 of FCR are ignored and an alternative arbitrary
receiver interrupt trigger level can be defined in the RTL
register. This 7bit value provides a fully programmable
receiver interrupt trigger facility as opposed to the limted
DataSheet Revision 1.1
Page 48
OX16PCI952
OXFORD SEMICONDUCTOR LTD.
trigger levels available in 16C650 and 16C750 devices. It
enables the systemdesigner to optimse the interrupt
performance hence mnimsing the interrupt overhead.
In 950 mode, a priority level 2 interrupt occurs indicating
that the receiver data is available when the interrupt is not
masked (IER[0]=1) and the receiver FIFO level reaches
the value stored in this register.
7.11.6 Flow Control Levels ‘FCL’ & ‘FCH’
The FCL and FCH registers are located at offsets 0x06 and
0x07 of the ICR respectively
Enhanced software flow control using XON/XOFF and
hardware flow control using RTS#/CTS# and DTR#/DSR#
are available when 950 mode trigger levels are enabled
(ACR[5]=1). Improved flow control threshold levels are
offered using Flow Control Lower trigger level (‘FCL’) and
Flow Control Higher trigger level (‘FCH’) registers to
provide a greater degree of flexibility when optimsing the
flow control performance. Generally, these facilities are
only available in Enhanced mode.
In 650 mode, in-band flow control is enabled using the EFR
register. An XOFF character may be transmtted when the
receiver FIFO exceeds the upper trigger level defined by
FCR[7:6] as described in section 7.4.1. An XON is then
sent when the FIFO is read down the lower fill level. The
flow control is enabled and the appropriate mode is
selected using EFR[3:0].
In 950 mode, the flow control thresholds defined by
FCR[7:6] are ignored. In this mode, threshold levels are
programmed using FCL and FCH. When flow control i
enabled by EFR[3:0] and the receiver FIFO level (‘RFL’)
reaches the value programmed in the FCH register, one
XOFF may be transmtted to stop the flow of serial data as
defined by EFR[3:0]. When the receiver FIFO level falls
below the value programmed in FCL, the flow is resumed
by sending one XON character (as defined in EFR[3:0]).
The FCL value of 0x00 is illegal.
CTS/RTS and DSR/DTR out-of-band flow control use the
same trigger levels as in-band flow control. When outof-
band flow control is enabled, RTS# (or DTR#) line is de-
asserted when the receiver FIFO level reaches the upper
limt defined in the FCH and is re-asserted when the
receiver FIFO is drained below a lower limt defined in FCL.
When 950 trigger levels are enabled (ACR[5]=1), the CTS#
fow control functions as in 650 mode and is configured by
EFR[7]. However, RTS# is automatically de-asserted and
re-asserted when EFR[6] is set and RFL reaches FCH and
drops below FCL. DSR# flow control is configured with
ACR[2]. DTR#flow control is configured with ACR[4:3].
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| OX16PCI952-TQFP-A | Integrated High Performance Dual UARTs, Parallel Port and 5.0v PCI interface |
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| OX4240 | OCXO |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| OX16PCI952_05 | 制造商:OXFORD 制造商全稱:OXFORD 功能描述:Integrated High Performance Dual UARTs, Parallel Port and 5.0v PCI interface |
| OX16PCI952-TQAG | 制造商:PLX Technology 功能描述: 制造商:Oxford Semiconductor 功能描述:IC PCI BRIDGE DUAL PORT UART SMD |
| OX16PCI952-TQC60-A | 制造商:OXFORD 制造商全稱:OXFORD 功能描述:Integrated High Performance Dual UARTs, Parallel Port and 5.0v PCI interface |
| OX16PCI952-TQFP-A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Integrated High Performance Dual UARTs, Parallel Port and 5.0v PCI interface |
| OX16PCI954 | 制造商:OXFORD 制造商全稱:OXFORD 功能描述:Integrated Quad UART and PCI interface |
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