參數(shù)資料
型號(hào)： OX16PCI952
廠商： Electronic Theatre Controls, Inc.
英文描述： Integrated High Performance Dual UARTs, Parallel Port and 5.0v PCI interface
中文描述： 集成高性能的雙UART，并行端口和5.0V PCI接口
文件頁(yè)數(shù)： 22/76頁(yè)
文件大?。?/td> 1386K
代理商： OX16PCI952
6.4.5
This register controls the assertion of interrupts and power management events, as well as returning the internal status of all
interrupt sources and power management events.
Bits
Description
0
UART 0 internal interrupt status
.
This bit reflects the state of UART 0’s internal interrupt line
1
.
1
UART 1 internal interrupt status
.
This bit reflects the state of UART 1’s internal interrupt line
1
.
2
MIO0 Internal State.
This bit reflects the state of the internal MIO[0] signal. The internal MIO[0]
signal reflects the non-inverted or inverted state of MIO0 pin.
2
3
MIO1 Internal State
This bit reflects the state of the internal MIO[1] signal. The internal MIO[1]
reflects the non-inverted or inverted state of MIO1 pin.
2
15:4
Reserved
.
16
UART 0 Interrupt Mask
.
When set (=1) this bit enables UART 0 to assert a PCI interrupt on function 0’s
interrupt pin (INTA# by default). When cleared (=0), UART 0 is prevented from
asserting a PCI interrupt.
3
17
UART 1 Interrupt Mask
.
When set (=1) this bit enables UART 1 to assert a PCI interrupt on function 0’s
interrupt pin (INTA# by default). When cleared (=0), UART 1 is prevented from
asserting a PCI interrupt.
3
18
MIO 0 Interrupt Mask
.
When set (=1) this bit enables the MIO 0 pin to assert a PCI interrupt, on the
selected functions interrupt pin. When cleared (=0) this prevents MIO 0 from
asserting a PCI interrupt.
The function that is affected is controlled by GIS, bit 26.
The MIO 0 pin is active high, unless inversion has been set in the MIC register
19
MIO 1 Interrupt Mask
.
When set (=1) this bit enables the MIO 1 pin to assert a PCI interrupt, on the
selected functions interrupt pin. When cleared (=0) this prevents MIO 1 from
asserting a PCI interrupt.
The function that is affected is controlled by GIS, bit 27.
The MIO 1 pin is active high, unless inversion has been set in the MIC register
20
MIO 0 Power-down Mask
.
When set (=1) this bit enables the MIO 0 pin to issue a powerdown event by
setting the selected functions power-down sticky bit (GIS, bits 22 or 23).
The function whose powerdown sticky bit is affected is controlled by GIS, bit
26.
Note that if the MIO 0 pin is routed to Function 0, then the pin uses the UART
power-down filtering algorithm Both the UARTs and the MIO 0 pin must
indicate a power-down for the filter period before any powerdown requests are
issued, for function 0. However, when the MIO 0 pin is routed to Function 1,
then a powerdown state on the pin MIO 0 will immediately issue a powerdown
request, for function 1, without any filters.
DataSheet Revision 1.1
Page 22
OX16PCI952
OXFORD SEMICONDUCTOR LTD.
Global Interrupt Status and Control Register ‘GIS’ (Offset 0x10)
Read/Write
EEPROM
-
Reset
0x0h
PCI
R
-
R
0x0h
-
R
X
-
R
X
-
W
R
RW
000h
1
W
RW
1
W
RW
0
W
RW
0
W
RW
0
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