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參數(shù)資料
| 型號： | OX16PCI952 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Integrated High Performance Dual UARTs, Parallel Port and 5.0v PCI interface |
| 中文描述： | 集成高性能的雙UART，并行端口和5.0V PCI接口 |
| 文件頁數(shù)： | 46/76頁 |
| 文件大?。?/td> | 1386K |
| 代理商： | OX16PCI952 |
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7.10.4 External 1x Clock Mode
The transmtter and receiver can accept an external clock
applied to the RI# and DSR# pns respectively. The clock
options are selected using the CKS register (see section
7.11.8). The transmtter and receiver may be configured to
operate in 1x (i.e. Isochronous mode) by setting CKS[7]
and CKS[3], respectively. In Isochronous mode, transmtter
or receiver will use the 1x clock (usually, but not
necessarily, an external source) where asynchronous
framng is maintained using start, parity- and stop-bits.
However serial transmssion and reception is synchronised
to the 1x clock. In this mode asynchronous data may be
transmtted at baud rates up to 60Mbps. The local 1x clock
source can be asserted on the DTR#pin.
Note that line drivers need to be capable of transmssion at
data rates twice the systemclock used (as one cycle of the
systemclock corresponds to 1 bit of serial data). Also note
that enabling modeminterrupts is illegal in isochronous
mode, as the clock signal will cause a continuous change
to the modemstatus (unless masked in MDMregister, see
section 7.11.10).
7.10.5 Crystal Oscillator Circuit
The UARTs reference reference clock may be provided by
its own crystal oscillator or directly froma clock source
7.11 Additional Features
DataSheet Revision 1.1
Page 46
OX16PCI952
OXFORD SEMICONDUCTOR LTD.
connected to the XTLI pin. The circuit required to use the
internal oscillator is shown in Figure 2.
R
1
R
2
C
1
C
2
XTLI
XTLO
Figure 2: Crystal Oscillator Circuit
Frequency
Range
(MHz)
1.8432 - 8
8-60
C
1
(pF)
C
2
(pF)
R
1
(
W
)
R
2
(
W
)
68
22
220k
220k-2M2
470R
470R
33-68
33 – 68
Table 24: Component values
Note: For better stability use a smaller value of R
1
.
Increase R
1
to reduce power consumption.
The total capacitive load (C1 in series with C2) should be
that specified by the crystal manufacturer (nomnally 16pF).
7.11.1 Additional Status Register ‘ASR’
ASR[0]: Transmitter disabled
logic 0
The transmtter is not disabled by in-band flow
control.
logic 1
The receiver has detected an XOFF, and has
disabled the transmtter.
This bit is cleared after a hardware reset or channel
software reset. The software driver may write a 0 to this bit
to re-enable the transmtter if it was disabled by in-band
flow control. Writing a 1 to this bit has no effect.
ASR[1]: Remote transmitter disabled
logic 0
The remote transmtter is not disabled by in-
band flow control.
logic 1
The transmtter has sent an XOFF character, to
disable the remote transmtter (cleared when
subsequent XON is sent).
This bit is cleared after a hardware reset or channel
software reset. The software driver may write a 0 to this bit
to re-enable the remote transmtter (an XON is
transmtted). Note: writing a 1 to this bit has no effect.
ASR[2]: RTS
This is the complement of the actual state of the RTS#pin
when the device is not in loopback mode. The driver
software can determne if the remote transmtter is disabled
by RTS# out-of-band flow control by reading this bit. In
loopback mode this bit reflects the flow control status rather
than the pins actual state.
ASR[3]: DTR
This is the complement of the actual state of the DTR#pin
when the device is not in loopback mode. The driver
software can determne if the remote transmtter is disabled
by DTR# out-of-band flow control by reading this bit. In
loopback mode this bitreflects the flow control status rather
than the pins actual state.
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