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參數(shù)資料
| 型號： | OX16PCI952 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Integrated High Performance Dual UARTs, Parallel Port and 5.0v PCI interface |
| 中文描述： | 集成高性能的雙UART，并行端口和5.0V PCI接口 |
| 文件頁數(shù)： | 14/76頁 |
| 文件大?。?/td> | 1386K |
| 代理商： | OX16PCI952 |
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6 PCI T
ARGET
C
ONTROLLER
DataSheet Revision 1.1
Page 14
OX16PCI952
OXFORD SEMICONDUCTOR LTD.
6.1
Operation
The OX16PCI952 responds to the following PCI
transactions:-
Configuration access
: The OX16PCI952 responds to
type 0 configuration reads and writes if the IDSEL
signal is asserted and the bus address selects the
configuration registers for function 0 or 1. The device
will respond to these configuration transactions by
asserting DEVSEL#. Data transfer then follows. Any
other configuration transaction will be ignored by the
OX16PCI952.
IO reads/writes
: The address is compared with the
addresses reserved in the I/O Base Address Registers
(BARs), of each available function. If the address falls
within one of the assigned ranges, the device will
respond to the IO transaction by asserting DEVSEL#.
Data transfer follows this address phase. For all
modes, only byte accesses are possible to the
function BARs (excluding the local configuration
registers for which WORD, DWORD access is
supported). For IO accesses to these regions, the
controller compares AD[1:0] with the byte-enable
signals as defined in the PCI specification. The access
is always completed; however if the correct BE signal
is not present the transaction will have no effect.
Memory reads/writes
: These are treated in the same
way as I/O transactions, except that the memory
ranges are used. With the exception of Memory
accesses to the local configuration registers, memory
access to single-byte regions such as the UART and
parallel port registers is always expanded to DWORDs
in the OX16PCI952. In other words, the OX16PCI952
reserves a DWORD per byte in single-byte regions.
The device allows the user to define the active byte
lane using LCC[4:3] so that in Big-Endian systems the
hardware can swap the byte lane automatically. For
Memory mapped access in single-byte regions, the
OX16PCI952 compares the asserted byte-enable with
the selected byte-lane in LCC[4:3] and completes the
operation if a match occurs, otherwise the access will
complete normally on the PCI bus, but it will have no
effect on the UART or the Parallel Port (if available).
All other cycles (64-bit, special cycles, reserved
encoding etc.) are ignored.
The OX16PCI952 will complete all transactions as
disconnectwith-data, ie the device will assert the STOP#
signal alongside TRDY# to ensure that the Bus Master
does not continue with a burst access. The exception to
this is Retry, which will be signalled in response to any
access while the OX16PCI952 is reading fromthe serial
EEPROM
The OX16PCI952 performs mediumspeed address
decoding as defined by the PCI specification. It asserts the
DEVSEL#bus signal two clocks after FRAME#is first
sampled low on all bus transaction frames which address
the chip. Fast back-to-back transactions (to both functions)
are supported by the OX16PCI952 as a target, so a bus
master can performfaster sequences of write transactions
(when an inter-frame turn-around cycle is not required) to
the UARTs, the Parallel Port, the PCI configuration space
and the local configuration registers. The internal UARTs
are accessed with zero wait states inserted.
The device supports any combination of byte-enables for
accesses to the PCI Configuration Registers and the Local
Configuration registers. If a byte-enable is not asserted,
that byte is unaffected by a write operation and undefined
data is returned upon a read.
The OX16PCI952 performs parity generation and checking
on all PCI bus transactions as defined by the PCI local Bus
standard.
Note that this is entirely unrelated to serial data
parity which is handled within the UART functional modules
themselves
. If a parity error occurs during the PCI bus
address phase, the device will report the error in the
standard way by asserting the SERR# bus signal. However
if that address/command combination is decoded as a valid
access, it will still complete the transaction as though the
parity check was correct.
The OX16PCI952 does not support any kind of caching or
data buffering in addition to that already provided within the
UARTs by the transmt and receive data FIFOs. In general,
data in the device cannot be pre-fetched because there
may be side-effects on reads.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| OX16PCI952-TQFP-A | Integrated High Performance Dual UARTs, Parallel Port and 5.0v PCI interface |
| OX16PCI954 | Integrated Quad UART and PCI interface |
| OX16PCI954-TQC60-A | Integrated Quad UART and PCI interface |
| OX4240 | OCXO |
| OX1040 | OCXO |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| OX16PCI952_05 | 制造商:OXFORD 制造商全稱:OXFORD 功能描述:Integrated High Performance Dual UARTs, Parallel Port and 5.0v PCI interface |
| OX16PCI952-TQAG | 制造商:PLX Technology 功能描述: 制造商:Oxford Semiconductor 功能描述:IC PCI BRIDGE DUAL PORT UART SMD |
| OX16PCI952-TQC60-A | 制造商:OXFORD 制造商全稱:OXFORD 功能描述:Integrated High Performance Dual UARTs, Parallel Port and 5.0v PCI interface |
| OX16PCI952-TQFP-A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Integrated High Performance Dual UARTs, Parallel Port and 5.0v PCI interface |
| OX16PCI954 | 制造商:OXFORD 制造商全稱:OXFORD 功能描述:Integrated Quad UART and PCI interface |
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