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參數(shù)資料
| 型號： | OX16PCI952 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Integrated High Performance Dual UARTs, Parallel Port and 5.0v PCI interface |
| 中文描述： | 集成高性能的雙UART，并行端口和5.0V PCI接口 |
| 文件頁數(shù)： | 50/76頁 |
| 文件大?。?/td> | 1386K |
| 代理商： | OX16PCI952 |
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9-bit mode. Note however that should an overrun or error
interrupt actually occur, an address character may also
reside in the FIFO. In this case, the software driver should
examne the contents of the receiver FIFO as well as
process the error.
The above facility produces an interrupt for recognizing any
‘a(chǎn)ddress’ characters. Alternatively, the user can configure
the UART to compare the receiver data streamwith up to
four programmable 9bit characters and assert a level 5
interrupt after detecting a match. The interrupt occurs when
the character is transferred to the FIFO (See below).
NMR[0]: 9-bit mode enable
logic 0
9-bit mode is disabled.
logic 1
9-bit mode is enabled.
NMR[1]: Enable interrupt when 9
th
bit is set
logic 0
Receiver interrupt for detection of an ‘a(chǎn)ddress’
character (i.e. 9
th
bit set) is disabled.
logic 1
Receiver interrupt for detection of an ‘a(chǎn)ddress’
character (i.e. 9
th
bit set) is enabled and a level
1 interrupt is asserted.
Special Character Detection
While the UART is in both 9-bit mode and Enhanced mode,
setting IER[5] will enable detection of up to four ‘a(chǎn)ddress’
characters. The least significant eight bits of these four
programmable characters are stored in special characters
1 to 4 (XON1, XON2, XOFF1 and XOFF2 in 650 mode)
registers and the 9
th
bit of these characters are
programmed in NMR[5] to NMR[2] respectively.
NMR[2]: Bit 9 of Special Character 1
NMR[3]: Bit 9 of Special Character 2
NMR[4]: Bit 9 of Special Character 3
NMR[5]: Bit 9 of Special Character 4
NMR[7:6]: Reserved
Bits 6 and 7 of NMR are always cleared and reserved for
future use.
7.11.10 Modem Disable Mask ‘MDM
The MDM register is located at offset 0x0E of the ICR
This register is cleared after a hardware reset to maintain
compatibility with 16C550. It allows the user to mask
interrupts, sleep operation and power management events
due to individual modemlines or the serial input line.
MDM[0]: Disable delta CTS
logic 0
Delta CTS is enabled. It can generate a level 4
interrupt when enabled by IER[3]. In power-
state D2, delta CTS can assert the PME#line.
Delta CTS can wake up the UART when it is
asleep under auto-sleep operation.
logic 1
Delta CTS is disabled. In can not generate an
interrupt, assert a PME# or wake up the UART.
DataSheet Revision 1.1
Page 50
OX16PCI952
OXFORD SEMICONDUCTOR LTD.
MDM[1]: Disable delta DSR
logic 0
Delta DSR is enabled. It can generate a level 4
interrupt when enabled by IER[3]. In power-
state D2, delta DSR can assert the PME#line.
Delta DSR can wake up the UART when it is
asleep under auto-sleep operation.
logic 1
Delta DSR is disabled. In can not generate an
interrupt, assert a PME# or wake up the UART.
MDM[2]: Disable Trailing edge RI
logic 0
Trailing edge RI is enabled. It can generate a
level 4 interrupt when enabled by IER[3]. In
power-state D2, trailing edge RI can assert the
PME#line. Trailing edge RI can wake up the
UART when it is asleep under auto-sleep
operation.
logic 1
Trailing edge RI is disabled. In can not
generate an interrupt, assert a PME#or wake
up the UART.
MDM[3]: Disable delta DCD
logic 0
Delta DCD is enabled. It can generate a level 4
interrupt when enabled by IER[3]. In power-
state D2, delta DCD can assert the PME#line.
Delta DCD can wake up the UART when it is
asleep under auto-sleep operation.
logic 1
Delta DCD is disabled. In can not generate an
interrupt, assert a PME# or wake up the UART.
MDM[4]: Reserved
This bit must be set to ‘0’
MDM[5]: Disable SIN wake up
logic 0
When the device is in power-down state D2, a
change in the state ofthe serial input line (i.e.
start bit) can assert the PME#line
logic 1
When the device is in power-down state D2, a
change in the state of the serial input line
cannot assert the PME#line.
MDM[7:6]: Reserved
7.11.11 Readable FCR ‘RFC’
The RFC register is located at offset 0x0F of the ICR
This read-only register returns the current state of the FCR
register (Note that FCR is write-only). This register is
included for diagnostic purposes.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| OX16PCI952-TQFP-A | Integrated High Performance Dual UARTs, Parallel Port and 5.0v PCI interface |
| OX16PCI954 | Integrated Quad UART and PCI interface |
| OX16PCI954-TQC60-A | Integrated Quad UART and PCI interface |
| OX4240 | OCXO |
| OX1040 | OCXO |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| OX16PCI952_05 | 制造商:OXFORD 制造商全稱:OXFORD 功能描述:Integrated High Performance Dual UARTs, Parallel Port and 5.0v PCI interface |
| OX16PCI952-TQAG | 制造商:PLX Technology 功能描述: 制造商:Oxford Semiconductor 功能描述:IC PCI BRIDGE DUAL PORT UART SMD |
| OX16PCI952-TQC60-A | 制造商:OXFORD 制造商全稱:OXFORD 功能描述:Integrated High Performance Dual UARTs, Parallel Port and 5.0v PCI interface |
| OX16PCI952-TQFP-A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Integrated High Performance Dual UARTs, Parallel Port and 5.0v PCI interface |
| OX16PCI954 | 制造商:OXFORD 制造商全稱:OXFORD 功能描述:Integrated Quad UART and PCI interface |
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