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| 型號(hào)： | OX16C954-TQC60-B |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | High Performance Quad UART with 128-byte FIFOs Intel / Motorola Bus Interface |
| 中文描述： | UART的高性能四路128字節(jié)的FIFO英特爾/摩托羅拉總線接口 |
| 文件頁(yè)數(shù)： | 47/54頁(yè) |
| 文件大小： | 529K |
| 代理商： | OX16C954-TQC60-B |
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Data Sheet Revision 1.0
Page 47
OX16C954 rev B
OXFORD SEMICONDUCTOR LTD.
18.2 3.3V Operation
N.B. Maximum frequency of operation is downgraded under 3V operation to 50 MHz
Symbol
Parameter
t
sa
Address set-up time to IOR#or IOW#falling
t
ha
Address hold time after IOR#or IOW#rising
t
sc
Chip-select set-up time to IOR#or IOW#falling
t
hc
Chip-select hold time after IOR#or IOW#rising
t
r1
Pulse duration of IOR#
t
r2
Delay time between IOR#rising and IOR#or IOW#falling
t
acc
Data valid after IOR#falling (access time)
t
hd
Data valid (hold) after IOR#rising
t
fd
Data bus floating after IOR#rising
t
w1
Pulse duration of IOW#
t
w2
Delay time between IOW#rising and IOR#or IOW#falling
t
sd
Data set-up time to IOW#rising
t
hd
Data hold time after IOW#rising
Mn
0
0
0
0
41
51
0
41
51
0
4
Max
32
14
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Table 26: Data bus timing for Intel mode
Symbol
t
sa
t
ha
t
srwr
t
hrwr
t
dr1
t
dr2
t
acc
t
dhr
t
fd
t
srww
t
hrww
t
dw1
t
dw2
t
sd
t
hdw
Parameter
Address set-up time to DS#falling
Address hold time after DS#rising
R/W# set-up time to DS#falling (read cycle)
R/W#hold time after DS#rising (read cycle)
Pulse duration of DS# (read cycle)
Delay to start of next read/write cycle (read cycle)
Read data valid after DS#falling (access time)
Read data hold data after DS#rising
Data bus float after DS#rising
R/W# set-up time to DS#falling (write cycle)
R/W#hold time after DS#rising (write cycle)
Pulse duration of DS# (write cycle)
Delay to start of next read/write cycle (write cycle)
Write data set-up time to DS#rising
Write data valid after DS#rising
Mn
5
0
5
0
41
51
0
5
0
41
51
0
4
Max
32
14
Units
Ns
Ns
Ns
Ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Table 27: Data bus timing for Motorola mode:
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