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參數(shù)資料
| 型號： | OX16C954-TQC60-B |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | High Performance Quad UART with 128-byte FIFOs Intel / Motorola Bus Interface |
| 中文描述： | UART的高性能四路128字節(jié)的FIFO英特爾/摩托羅拉總線接口 |
| 文件頁數(shù)： | 25/54頁 |
| 文件大?。?/td> | 529K |
| 代理商： | OX16C954-TQC60-B |
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Data Sheet Revision 1.0
Page 25
OX16C954 rev B
OXFORD SEMICONDUCTOR LTD.
LCR[1:0]: Data length
LCR[1:0] Determnes the data length of serial characters.
Note however, that these values are ignored in 9-bit data
framng mode, i.e. when NMR[0] is set.
LCR[1:0]
00
01
10
11
Data length
5 bits
6 bits
7 bits
8 bits
Table 11: LCR Data Length Configuration
LCR[2]: Number of stop bits
LCR[2] defines the number of stop bits per serial character.
LCR[2]
Data length
No. stop
bits
1
1.5
2
0
1
1
5,6,7,8
5
6,7,8
Table 12: LCR Stop Bit Number Configuration
LCR[5:3]: Parity type
The selected parity type will be generated during
transmssion and checked by the receiver, which may
produce a parity error as a result. In 9-bit mode parity is
disabled and LCR[5:3] is ignored.
LCR[5:3]
xx0
001
011
101
Parity bit forced to 1
111
Parity bit forced to 0
Parity type
No parity bit
Odd parity bit
Even parity bit
Table 13: LCR Parity Configuration
LCR[6]: Transmission break
logic 0
Break transmssion disabled.
logic 1
Forces the transmtter data output SOUT low
to alert the communication termnal, or send
zeros in IrDA mode.
It is the responsibility of the software driver to ensure that
the break duration is longer than the character period for it
to be recognised remotely as a break rather than data.
LCR[7]: Divisor latch enable
logic 0
Access to DLL and DLMregisters disabled.
logic 1
Access to DLL and DLMregisters enabled.
9.3
This register provides the status of data transfer to CPU.
LSR[0]: RHR data available
logic 0
RHR is empty: no data available
logic 1
RHR is not empty: data is available to be read.
LSR[1]: RHR overrun error
logic 0
No overrun error.
logic 1
Data was received when the RHR was full. An
overrun error has occurred. The error is flagged
when the data would normally have been
transferred to the RHR.
LSR[2]: Received data parity error
logic 0
No parity error in normal mode or 9
th
bit of
received data is ‘0’ in 9-bit mode.
logic 1
Data has been received that did not have
correct parity in normal mode or 9
th
bit of
received data is ‘1’ in 9-bit mode.
The flag will be set when the data itemin error is at the top
of the RHR and cleared following a read of the LSR. In 9-
bit mode LSR[2] is no longer a flag and corresponds to the
9
th
bit of the received data in RHR.
LSR[3]: Received data framing error
logic 0
No framng error.
logic 1
Data has been received with an invalid stop bit.
This status bit is set and cleared in the same manner as
LSR[2]. When a framng error occurs, the UART will try to
re-synchronise by assumng that the error was due to
sampling the start bit of the next data item
LSR[4]: Received break error
logic 0
No receiver break error.
logic 1
The receiver received a break.
A break condition occurs when the SIN line goes low
(normally signifying a start bit) and stays low throughout
the start, data, parity and first stop bit. (Note that the SIN
line is sampled at the bit rate). One zero character with
associated break flag set will be transferred to the RHR
and the receiver will then wait until the SIN line returns
high. The LSR[4] break flag will be set when this data item
gets to the top of the RHR and it is cleared following a read
of the LSR.
LSR[5]: THR empty
logic 0
Transmtter FIFO (THR) is not empty.
logic 1
Transmtter FIFO (THR) is empty.
Line Status Register ‘LSR’
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