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參數(shù)資料
| 型號(hào)： | OX16C954-TQC60-B |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | High Performance Quad UART with 128-byte FIFOs Intel / Motorola Bus Interface |
| 中文描述： | UART的高性能四路128字節(jié)的FIFO英特爾/摩托羅拉總線接口 |
| 文件頁數(shù)： | 38/54頁 |
| 文件大?。?/td> | 529K |
| 代理商： | OX16C954-TQC60-B |
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Data Sheet Revision 1.0
Page 38
OX16C954 rev B
OXFORD SEMICONDUCTOR LTD.
ACR[1]: Transmitter disable
logic 0
The transmtter is enabled, transmtting any
data in the THR.
logic 1
The transmtter is disabled. Any data in the
THR is not transmtted but is held. However, in-
band flow control characters may still be
transmtted.
Changes to this bit will only be recognised following the
completion of any data transmssion pending.
ACR[2]: Enable automatic DSR flow control
logic 0
Normal. The state of the DSR#line does not
affect the flow control.
logic 1
Data transmssion is prevented whenever the
DSR#pin is held inactive high.
This bit provides another automatic out-of-band flow control
facility using the DSR#line.
ACR[4:3]: DTR#line configuration
When bits 4 or 5 of CKS (offset 0x03 of ICR) are set, the
transmtter 1x clock or the output of the baud rate
generator (Nx clock) are asserted on the DTR#pin,
otherwise the DTR#pin is defined as follows:
logic [00]
DTR#is compatible with 16C450, 16C550,
16C650 and 16C750 (i.e. normal).
logic [01]
DTR#pin is used for out-of-band flow control.
It will be forced inactive high if the Receiver
FIFO Level (‘RFL’) reaches the upper flow
control threshold. DTR#line will be re-
activated (=0) when the RFL drops below the
lower threshold (see FCL & FCH).
logic [10]
DTR#pin is configured to drive the active-low
enable pin of an external RS485 buffer. In
this configuration the DTR#pin will be forced
low whenever the transmtter is not empty
(LSR[6]=0), otherwise DTR#pin is high.
logic [11]
DTR#pin is configured to drive the active-
high enable pin of an external RS485 buffer.
In this configuration, the DTR#pin will be
forced high whenever the transmtter is not
empty (LSR[6]=0), otherwise DTR#pin is low.
If the user sets ACR[4], then the DTR#line is controlled by
the status of the transmtter empty bit of LCR. When
ACR[4] is set, ACR[3] is used to select active high or active
low enable signals. In half-duplex systems using RS485
protocol, this facility enables the DTR#line to directly
control the enable signal of external 3-state line driver
buffers. When the transmtter is empty the DTR#would go
inactive once the SOUT line returns to it’s idle marking
state.
ACR[5]: 950 mode trigger levels enable
logic 0
Interrupts and flow control trigger levels are as
described in FCR register and are compatible
with 16C650/16C750 modes.
logic 1
950 specific enhanced interrupt and flow
control trigger levels defined by RTL, TTL, FCL
and FCH are enabled.
ACR[6]: ICR read enable
logic 0
The Line Status Register is readable.
logic 1
The Indexed Control Registers are readable.
Setting this bit will map the ICR set to the LSR location for
reads. During normal operation this bit should be cleared.
ACR[7]: Additional status enable
logic 0
Access to the ASR, TFL and RFL registers is
disabled.
logic 1
Access to the ASR, TFL and RFL registers is
enabled.
When ACR[7] is set, the MCR and LCR registers are no
longer readable but remain writable, and the TFL and RFL
registers replace themin the memory map for read
operations. The IER register is replaced by the ASR
register for all operations. The software driver may leave
this bit set during normal operation, since MCR, LCR and
IER do not generally need to be read.
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