參數(shù)資料
型號(hào)： OX16C954-TQC60-B
廠商： Electronic Theatre Controls, Inc.
英文描述： High Performance Quad UART with 128-byte FIFOs Intel / Motorola Bus Interface
中文描述： UART的高性能四路128字節(jié)的FIFO英特爾/摩托羅拉總線接口
文件頁(yè)數(shù)： 41/54頁(yè)
文件大?。?/td> 529K
代理商： OX16C954-TQC60-B
Data Sheet Revision 1.0
Page 41
OX16C954 rev B
OXFORD SEMICONDUCTOR LTD.
NMR[0]: 9-bit mode enable
logic 0
9-bit mode is disabled.
logic 1
9-bit mode is enabled.
NMR[1]: Enable interrupt when 9
th
bit is set
logic 0
Receiver interrupt for detection of an ‘a(chǎn)ddress’
character (i.e. 9
th
bit set) is disabled.
logic 1
Receiver interrupt for detection of an ‘a(chǎn)ddress’
character (i.e. 9
th
bit set) is enabled and a level
1 interrupt is asserted.
Special Character Detection
While the UART is in both 9-bit mode and Enhanced mode,
setting IER[5] will enable detection of up to four ‘a(chǎn)ddress’
characters. The least significant eight bits of these four
programmable characters are stored in special characters
1 to 4 (XON1, XON2, XOFF1 and XOFF2 in 650 mode)
registers and the 9
th
bit of these characters are
programmed in NMR[5] to NMR[2] respectively.
NMR[2]: Bit 9 of Special Character 1
NMR[3]: Bit 9 of Special Character 2
NMR[4]: Bit 9 of Special Character 3
NMR[5]: Bit 9 of Special Character 4
NMR[7:6]: Reserved
Bits 6 and 7 of NMR are always cleared and reserved for
future use.
15.10 Modem Disable Mask ‘MDM
The MDMregister is located at offset 0x0E of the ICR
This register is cleared after a hardware reset to maintain
compatibility with 16C550. It allows the user to mask
interrupts, sleep operation due to individual modemlines or
the serial input line.
MDM[0]: Disable delta CTS
logic 0
Delta CTS is enabled. It can generate a level 4
interrupt when enabled by IER[3]. Delta CTS
can wake up the UART when it is asleep under
auto-sleep operation.
logic 1
Delta CTS is disabled. It can not generate an
interrupt or wake up the UART.
MDM[1]: Disable delta DSR
logic 0
Delta DSR is enabled. It can generate a level 4
interrupt when enabled by IER[3]. Delta DSR
can wake up the UART when it is asleep under
auto-sleep operation.
logic 1
Delta DSR is disabled. It can not generate an
interrupt or wake up the UART.
MDM[2]: Disable Trailing edge RI
logic 0
Trailing edge RI is enabled. It can generate a
level 4 interrupt when enabled by IER[3].
Trailing edge RI can wake up the UART when it
is asleep under auto-sleep operation.
logic 1
Trailing edge RI is disabled. It can not
generate an interrupt or wake up the UART.
MDM[3]: Disable delta DCD
logic 0
Delta DCD is enabled. It can generate a level 4
interrupt when enabled by IER[3]. Delta DCD
can wake up the UART when it is asleep under
auto-sleep operation.
logic 1
Delta DCD is disabled. It can not generate an
interrupt or wake up the UART.
MDM[7:4]: Reserved
These bits must be set to ‘0000’
15.11 Readable FCR ‘RFC’
The RFC register is located at offset 0x0F of the ICR
This read-only register returns the current state of the FCR
register (Note that FCR is write-only). This register is
included for diagnostic purposes.
15.12 Good-data status register ‘GDS’
The GDS register is located at offset 0x10 of the ICR
Good data status is set when the following conditions are
true:
ISR reads level0 (no interrupt), level 2 or 2a
(receiver data) or level 3 (THR empty) interrupt.
LSR[7] is clear i.e. no parity error, framng error
or break in the fifo.
LSR[1] is clear i.e. no overrun error has occurred.
GDS[0]: Good Data Status
GDS[7:1]: Reserved
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