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參數(shù)資料
| 型號： | OX16C954-TQC60-B |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | High Performance Quad UART with 128-byte FIFOs Intel / Motorola Bus Interface |
| 中文描述： | UART的高性能四路128字節(jié)的FIFO英特爾/摩托羅拉總線接口 |
| 文件頁數(shù)： | 39/54頁 |
| 文件大小： | 529K |
| 代理商： | OX16C954-TQC60-B |
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Data Sheet Revision 1.0
Page 39
OX16C954 rev B
OXFORD SEMICONDUCTOR LTD.
15.4 Transmitter Trigger Level ‘TTL’
The TTL register is located at offset 0x04 of the ICR
Whenever 950 trigger levels are enabled (ACR[5]=1), bits 4
and 5 of FCR are ignored and an alternative arbitrary
transmtter interrupt trigger level can be defined in the TTL
register. This 7-bit value provides a fully programmable
transmtter interrupt trigger facility. In 950 mode, a priority
level 3 interrupt occurs indicating that the transmtter buffer
requires more characters when the interrupt is not masked
(IER[1]=1) and the transmtter FIFO level falls below the
value stored in the TTL register. The value 0 (0x00) has a
special meaning. In 950 mode when the user writes 0x00
to the TTL register, a level 3 interrupt only occurs when the
FIFO and the transmtter shift register are both empty and
the SOUT line is in the idle marking state. This feature is
particularly useful to report back the empty state of the
transmtter after its FIFO has been flushed away.
15.5 Receiver Interrupt. Trigger Level ‘RTL’
The RTL register is located at offset 0x05 of the ICR
Whenever 950 trigger levels are enabled (ACR[5]=1), bits 6
and 7 of FCR are ignored and an alternative arbitrary
receiver interrupt trigger level can be defined in the RTL
register. This 7-bit value provides a fully programmable
receiver interrupt trigger facility as opposed to the limted
trigger levels available in 16C650 and 16C750 devices. It
enables the systemdesigner to optimse the interrupt
performance hence mnimsing the interrupt overhead.
In 950 mode, a priority level 2 interrupt occurs indicating
that the receiver data is available when the interrupt is not
masked (IER[0]=1) and the receiver FIFO level reaches
the value stored in this register.
15.6 Flow Control Levels ‘FCL’ & ‘FCH’
The FCL and FCH registers are located at offsets 0x06 and
0x07 of the ICR respectively
Enhanced software flow control using XON/XOFF and
hardware flow control using RTS#/CTS#and DTR#/DSR#
are available when 950 mode trigger levels are enabled
(ACR[5]=1). Improved flow control threshold levels are
offered using Flow Control Lower trigger level (‘FCL’) and
Flow Control Higher trigger level (‘FCH’) registers to
provide a greater degree of flexibility when optimsing the
flow control performance. Generally, these facilities are
only available in Enhanced mode.
In 650 mode, in-band flow control is enabled using the EFR
register. An XOFF character may be transmtted when the
receiver FIFO exceeds the upper trigger level defined by
FCR[7:6] as described in section 8.1. An XON is then sent
when the FIFO is read down the lower fill level. The flow
control is enabled and the appropriate mode is selected
using EFR[3:0].
In 950 mode, the flow control thresholds defined by
FCR[7:6] are ignored. In this mode, threshold levels are
programmed using FCL and FCH. When in-band flow
control is enabled (defined by EFR[3:0]) and the receiver
FIFO level (‘RFL’) reaches the value programmed in the
FCH register, an XOFF is transmtted to stop the flow of
serial data. The flow is resumed when the receiver FIFO fill
level falls below the value programmed in FCL, at which
point an XON character is sent. The FCL value of 0x00 is
illegal.
For example if FCL and FCH contain 64 and 100
respectively, XOFF is transmtted when the receiver FIFO
contains 100 characters, and XON is transmtted when
sufficient characters are read fromthe receiver FIFO such
that there are 63 characters remaining.
CTS/RTS and DSR/DTR out-of-band flow control use the
same trigger levels as in-band flow control. When out-of-
band flow control is enabled, RTS#(or DTR#) line is de-
asserted when the receiver FIFO level reaches the upper
limt defined in the FCH and is re-asserted when the
receiver FIFO is drained below the lower limt defined in
FCL. When 950 trigger levels are enabled (ACR[5]=1), the
CTS#flow control functions as in 650 mode and is
configured by EFR[7]. However, when EFR[6] is set, RTS#
is automatically de-asserted whemRFL traches FCH and
re-asserted when RFL drops below FCL.
DSR#flow control is configured with ACR[2]. DTR#flow
control is configured with ACR[4:3].
15.7 Device Identification Registers
The identification registers are located at offsets 0x08 to
0x0B of the ICR
The UARTs offer four bytes of device identification. The
device ID registers may be read using offset values 0x08 to
0x0B of the Indexed Control Register. Registers ID1, ID2
and ID3 identify the device as an OX16C954 and return
0x16, 0xC9 and 0x54 respectively. The REV register
resides at offset 0x0B of ICR and identifies the revision of
950 core. This register returns 0x04 for the UART core in
this device.
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