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參數(shù)資料
| 型號： | OX16C954-TQC60-B |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | High Performance Quad UART with 128-byte FIFOs Intel / Motorola Bus Interface |
| 中文描述： | UART的高性能四路128字節(jié)的FIFO英特爾/摩托羅拉總線接口 |
| 文件頁數(shù)： | 30/54頁 |
| 文件大?。?/td> | 529K |
| 代理商： | OX16C954-TQC60-B |
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Data Sheet Revision 1.0
Page 30
OX16C954 rev B
OXFORD SEMICONDUCTOR LTD.
12 O
THER
S
TANDARD
R
EGISTERS
12.1 Divisor Latch Registers ‘DLL & DLM
The divisor latch registers are used to programthe baud
rate divisor. This is a value between 1 and 65535 by which
the input clock is divided by in order to generate serial
baud rates. After a hardware reset, the baud rate used by
the transmtter and receiver is given by:
Divisor
InputClock
*
16
Baudrate
=
Where divisor is given by DLL + ( 256 x DLM). More
flexible baud rate generation options are also available.
See section 14 for full details.
12.2 Scratch Pad Register ‘SPR’
The scratch pad register does not affect operation of the
rest of the UART in any way and can be used for
temporary data storage. The register may also be used to
define an offset value to access the registers in the
Indexed Control Register set. For more information on
Indexed Control registers see Table 7and section 15.
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