參數(shù)資料
型號: OX16C954-TQC60-B
廠商: Electronic Theatre Controls, Inc.
英文描述: High Performance Quad UART with 128-byte FIFOs Intel / Motorola Bus Interface
中文描述: UART的高性能四路128字節(jié)的FIFO英特爾/摩托羅拉總線接口
文件頁數(shù): 33/54頁
文件大?。?/td> 529K
代理商: OX16C954-TQC60-B
Data Sheet Revision 1.0
Page 33
OX16C954 rev B
OXFORD SEMICONDUCTOR LTD.
14 B
AUD
R
ATE
G
ENERATION
14.1 General Operation
The UART contains a programmable baud rate generator
that is capable of taking any clock input from1.8432MHz to
60MHz (at 5V) and dividing it by any 16-bit divisor number
from1 to 65535 written into the DLM(MSB) and DLL (LSB)
registers. In addition to this, a clock prescaler register is
provided which can further divide the clock by values in the
range 1.0 to 31.875 in steps of 0.125. Also, a further
feature is the Times Clock Register ‘TCR’ which allows the
sampling clock to be set to any value between 4 and 16.
These clock options allow for highly flexible baud rate
generation capabilities fromalmost any input clock
frequency (up to 60MHz). The actual transmtter and
receiver baud rate is calculated as follows:
InputClock
BaudRate
*
Where
:
SC
= Sample clock values defined in TCR[3:0]
Divisor = DLL + ( 256 x DLM)
Prescaler = 1 when MCR[7] = ‘0’ else:
= M+ ( N / 8 ) where:
M
= CPR[7:3] (Integer part – 1 to 31)
N
= CPR[2:0] (Fractional part – 0.000 to 0.875 )
See the next section for a discussion of the clock prescaler
and times clock register.
After a hardware reset, the prescaler is bypassed (set to 1)
and TCR is set to 0x00 (i.e. SC = 16). Assumng this
default configuration, the following table gives the divisors
required to be programmed into the DLL and DLMregisters
in order to obtain various standard baud rates:
prescaler
Divisor
SC
*
=
DLMDLL
Divisor Word
0x0900
0x0300
0x0180
0x00C0
0x0060
0x0030
0x0018
0x000C
0x0006
0x0004
0x0003
0x0002
0x0001
Baud Rate
(bits per second)
50
110
300
600
1,200
2,400
4,800
9,600
19,200
28,800
38,400
57,600
115,200
Table 15: Standard PC COMPort Baud Rate Divisors
(assuming a 1.8432MHz crystal)
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