參數(shù)資料
型號(hào)： OX16C954-TQC60-B
廠商： Electronic Theatre Controls, Inc.
英文描述： High Performance Quad UART with 128-byte FIFOs Intel / Motorola Bus Interface
中文描述： UART的高性能四路128字節(jié)的FIFO英特爾/摩托羅拉總線接口
文件頁(yè)數(shù)： 26/54頁(yè)
文件大?。?/td> 529K
代理商： OX16C954-TQC60-B
Data Sheet Revision 1.0
Page 26
OX16C954 rev B
OXFORD SEMICONDUCTOR LTD.
LSR[6]: Transmitter and THR empty
logic 0
The transmtter is not idle
logic 1
THR is empty and the transmtter has
completed the character in shift register and is
in idle mode. (I.e. set whenever the transmtter
shift register and the THR are both empty.)
LSR[7]: Receiver data error
logic 0
Either there are no receiver data errors in the
FIFO or it was cleared by an earlier read of
LSR.
10 I
NTERRUPTS
& S
LEEP
M
ODE
logic 1
At least one parity error, framng error or break
indication in the FIFO.
In 450 mode LSR[7] is permanently cleared, otherwise this
bit will be set when an erroneous character is transferred
fromthe receiver to the RHR. It is cleared when the LSR is
read.
Note that in 16C550 this bit is only cleared when
all of the erroneous data are removed from the FIFO
. In
9-bit data framng mode parity is permanently disabled, so
this bit is not affected by LSR[2].
In Intel mode, the serial channel interrupts are asserted on
the respective INT pin. When INTSEL#is high the INT pin
is permanently enabled and MCR[3] is ignored. When
INTSEL#is low or unconnected, the tri-state control of INT
is controlled by MCR[3] (enabled when MCR[3] is set, high-
impedance state when MCR[3] is cleared).
In Motorola mode, all channel interrupts are ORed together
and asserted on the IRQ#pin. The INTSEL#pin has no
effect in this mode. The tri-state control of each channels
interrupt is controlled by MCR[3]. Any non-tristated channel
interrupt causes IRQ#to be asserted.
10.1 Interrupt Enable Register ‘IER’
Serial channel interrupts are enabled using the Interrupt
Enable Register (‘IER’).
IER[0]: Receiver data available interrupt mask
logic 0
Disable the receiver ready interrupt.
logic 1
Enable the receiver ready interrupt.
IER[1]: Transmitter empty interrupt mask
logic 0
Disable the transmtter empty interrupt.
logic 1
Enable the transmtter empty interrupt.
IER[2]: Receiver status interrupt
Normal mode:
logic 0
Disable the receiver status interrupt.
logic 1
Enable the receiver status interrupt.
9-bit data mode:
logic 0
Disable receiver status and address bit
interrupt.
logic 1
Enable receiver status and address bit
interrupt.
In 9-bit mode (i.e. when NMR[0] is set), reception of a
character with the address-bit (i.e. 9
th
bit) set can generate
a level 1 interrupt if IER[2] is set.
IER[3]: Modem status interrupt mask
logic 0
Disable the modemstatus interrupt.
logic 1
Enable the modemstatus interrupt.
IER[4]: Sleep mode
logic 0
Disable sleep mode.
logic 1
Enable sleep mode whereby the internal clock
of the channel is switched off.
Sleep mode is described in section 10.4.
IER[5]: Special character interrupt mask or alternate
sleep mode
9-bit data framng mode:
logic 0
Disable the received special character interrupt.
logic 1
Enable the received special character interrupt.
In 9-bit data mode, The receiver can detect up to four
special characters programmed in the Special Character
Registers (see map on page 19). When IER[5] is set, a
level 5 interrupt is asserted when the receiver character
matches one of the values programmed.
650/950 modes (non-9-bit data framng):
logic 0
Disable the special character receive interrupt.
logic 1
Enable the special character receive interrupt.
In 16C650 compatible mode when the device is in
Enhanced mode (EFR[4]=1), this bit enables the detection
of special characters. It enables both the detection of
XOFF characters (when in-band flow control is enabled via
EFR[3:0]) and the detection of the XOFF2 special
character (when enabled via EFR[5]).
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