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參數(shù)資料
| 型號： | OX16C954-TQC60-B |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | High Performance Quad UART with 128-byte FIFOs Intel / Motorola Bus Interface |
| 中文描述： | UART的高性能四路128字節(jié)的FIFO英特爾/摩托羅拉總線接口 |
| 文件頁數(shù)： | 31/54頁 |
| 文件大?。?/td> | 529K |
| 代理商： | OX16C954-TQC60-B |
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Data Sheet Revision 1.0
Page 31
OX16C954 rev B
OXFORD SEMICONDUCTOR LTD.
13 A
UTOMATIC
F
LOW
C
ONTROL
Automatic in-band flow control, automatic out-of-band flow
control and special character detection features can be
used when in Enhanced mode and are software compatible
with the 16C654. Alternatively, 750-compatible automatic
out-of-band flow control can be enabled when in non-
Enhanced mode. In 950 mode, in-band and out-of-band
flow controls are compatible with 16C654 with the addition
of fully programmable flow control thresholds.
13.1 Enhanced Features Register ‘EFR’
Writing 0xBF to LCR enables access to the EFR and other
Enhanced mode registers. This value corresponds to an
unused data format. Writing 0xBF to LCR will set LCR[7]
but leaves LCR[6:0] unchanged. Therefore, the data format
of the transmtter and receiver data is not affected. Write
the desired LCR value to exit fromthis selection.
Note: In-band transmt and receive flow control is disabled
in 9-bit mode.
EFR[1:0]: In-band receive flow control mode
When in-band receive flow control is enabled, the UART
compares the received data with the programmed XOFF
character. When this occurs, the UART will disable
transmssion as soon as any current character
transmssion is complete. The UART then compares the
received data with the programmed XON character. When
a match occurs, the UART will re-enable transmssion (see
section 15.6).
For automatic in-band flow control, bit 4 of EFR must be
set. The combinations of software receive flow control can
be selected by programmng EFR[1:0] as follows:
logic [00]
In-band receive flow control is disabled.
logic [01]
Single character in-band receive flow control
enabled, recognising XON2 as the XON
character and XOFF2 as the XOFF
character.
logic [10]
Single character in-band receive flow control
enabled, recognising XON1 as the XON
character and XOFF1 as the XOFF
character.
logic [11]
The behaviour of the receive flow control is
dependent on the configuration of EFR[3:2].
Single character in-band receive flow control
is enabled, accepting XON1 or XON2 as valid
XON characters and XOFF1 or XOFF2 as
valid XOFF characters when EFR[3:2] = “01”
or “10”. EFR[1:0] should not be set to “11”
when EFR[3:2] is ‘00’.
EFR[3:2]: In-band transmit flow control mode
When in-band transmt flow control is enabled, an
XON/XOFF character is inserted into the data stream
whenever the RFL passes the upper trigger level and falls
below the lower trigger level respectively.
For automatic in-band flow control, bit 4 of EFR must be
set. The combinations of software transmt flow control can
then be selected by programmng EFR[3:2] as follows:
logic [00]
In-band transmt flow control is disabled.
logic [01]
Single character in-band transmt flow control
enabled, using XON2 as the XON character
and XOFF2 as the XOFF character.
logic [10]
Single character in-band transmt flow control
enabled, using XON1 as the XON character
and XOFF1 as the XOFF character.
logic[11]
The value EFR[3:2] = “11” is reserved for
future use and should not be used
EFR[4]: Enhanced mode
logic 0
Non-Enhanced mode. Disables IER bits 4-7,
ISR bits 4-5, FCR bits 4-5, MCR bits 5-7 and in-
band flow control. Whenever this bit is cleared,
the setting of other bits of EFR are ignored.
logic 1
Enhanced mode. Enables the Enhanced Mode
functions. These functions include enabling
IER bits 4-7, FCR bits 4-5, MCR bits 5-7. For
in-band flow control the software driver must
set this bit first. If this bit is set, out-of-band flow
control is configured with EFR bits 6-7,
otherwise out-of-band flow control is compatible
with 16C750.
EFR[5]: Enable special character detection
logic 0
Special character detection is disabled.
logic 1
While in Enhanced mode (EFR[4]=1), the
UART compares the incomng receiver data
with the XOFF2 value. Upon a correct match,
the received data will be transferred to the RHR
and a level 5 interrupt (XOFF or special
character) will be asserted if level 5 interrupts
are enabled (IER[5] set to 1).
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