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參數(shù)資料
| 型號(hào)： | OX16C954-TQC60-B |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | High Performance Quad UART with 128-byte FIFOs Intel / Motorola Bus Interface |
| 中文描述： | UART的高性能四路128字節(jié)的FIFO英特爾/摩托羅拉總線接口 |
| 文件頁數(shù)： | 28/54頁 |
| 文件大?。?/td> | 529K |
| 代理商： | OX16C954-TQC60-B |
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Data Sheet Revision 1.0
Page 28
OX16C954 rev B
OXFORD SEMICONDUCTOR LTD.
Level 4:
Modem change interrupt (ISR[5:0]=’000000’):
This interrupt is set by a modemchange flag (MSR[0],
MSR[1], MSR[2] or MSR[3]) becomng active due to
changes in the input modemlines. This interrupt is cleared
following a read of the MSR.
Level 5:
Receiver in-band flow control (XOFF) detect interrupt,
Receiver special character (XOFF2) detect interrupt,
Receiver special character 1, 2, 3 or 4 interrupt or
9
th
Bit set interrupt in 9-bit mode (ISR[5:0]=’010000’):
A level 5 interrupt can only occur in Enhanced-mode when
any of the following conditions are met:
A valid XOFF character is received while in-band flow
control is enabled.
A received character matches XOFF2 while special
character detection is enabled, i.e. EFR[5]=1.
A received character matches special character 1, 2, 3
or 4 in 9-bit mode (see section 15.9).
It is cleared on an ISR read of a level 5 interrupt.
Level 6:
CTS or RTS changed interrupt (ISR[5:0]=’100000’):
This interrupt is set whenever any of the CTS#or RTS#
pins changes state fromlow to high. It is cleared on an ISR
read of a level 6 interrupt.
11 M
ODEM
I
NTERFACE
10.4 Sleep Mode
For a channel to go into sleep mode, all of the following
conditions must be met:
Sleep mode enabled (IER[4]=1 in 650/950 modes, or
IER[5]=1 in 750 mode):
The transmtter is idle, i.e. the transmtter shift register
and FIFO are both empty.
SIN is high.
The receiver is idle.
The receiver FIFO is empty (LSR[0]=0).
The UART is not in loopback mode (MCR[4]=0).
Changes on modeminput lines have been
acknowledged (i.e. MSR[3:0]=0000).
No interrupts are pending.
A read of IER[4] (or IER[5] if a 1 was written to that bit
instead) shows whether the power-down request was
successful. The UART will fully retain its programmed state
whilst in power-down mode.
The channel will automatically exit power-down mode when
any of the conditions 1 to 7 becomes false. It may be
woken manually by clearing IER[4] (or IER[5] if the
alternate sleep mode is enabled).
Sleep mode operation is not available in IrDA mode.
11.1 Modem Control Register ‘MCR’
MCR[0]: DTR
logic 0
Force DTR#output to inactive (high).
logic 1
Force DTR#output to active (low).
Note that DTR#can be used for automatic out-of-band flow
control when enabled using ACR[4:3] (see section 15.3).
MCR[1]: RTS
logic 0
Force RTS#output to inactive (high).
logic 1
Force RTS#output to active (low).
Note that RTS#can be used for automatic out-of-band flow
control when enabled using EFR[6] (see section 13.4).
MCR[2]: OUT1
Writing this bit will have no affect on operation. Reading
this bit will return the last value written. This bit is only used
for test purposes in local loop-back mode (MCR[4] = ‘1’).
MCR[3]: OUT2 / External interrupt enable
logic 0
The interrupt pin is in high-impedance state
and will never be asserted
logic 1
The interrupt pin is enabled and will be
asserted when interrupts occur.
Used for test in local loop-back mode(MCR[4] = ‘1’)
Note: In Intel mode, the INTSEL#pin must also be low. When
INTSEL#is high, interrupts are permanently enabled in this
mode.
MCR[4]: Loopback mode
logic 0
Normal operating mode.
logic 1
Enable local loop-back mode (diagnostics).
In local loop-back mode, the transmtter output (SOUT) and
the two modemoutputs (DTR# RTS#) are set in-active
(high), and the receiver inputs SIN, CTS# DSR# DCD#
and RI#are all disabled. Internally the transmtter output is
connected to the receiver input and DTR# RTS# OUT1#
and OUT2#are connected to modemstatus inputs DSR#
CTS#, RI#and DCD#respectively.
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