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參數(shù)資料
| 型號： | OR4E4 |
| 廠商： | Lineage Power |
| 英文描述： | Field-Programmable Gate Arrays(現(xiàn)場可編程門陣列) |
| 中文描述： | 現(xiàn)場可編程門陣列（現(xiàn)場可編程門陣列） |
| 文件頁數(shù)： | 55/132頁 |
| 文件大?。?/td> | 2667K |
| 代理商： | OR4E4 |
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Preliminary Data Sheet
August 2000
Lucent Technologies Inc.
55
ORCA Series 4 FPGAs
FPGA States of Operation
Prior to becoming operational, the FPGA goes through a sequence of states, including initialization, configuration,
and start-up. Figure 33 outlines these three states.
5-4529(F).
Figure 33. FPGA States of Operation
– ACTIVE I/O
– RELEASE INTERNAL RESET
– DONE GOES HIGH
START-UP
INITIALIZATION
CONFIGURATION
RESET
OR
PRGM
LOW
PRGM
LOW
– CLEAR CONFIGURATION MEMORY
– INIT LOW, HDC HIGH, LDC LOW
OPERATION
POWERUP
– POWER-ON TIME DELAY
– M[3:0] MODE IS SELECTED
– CONFIGURATION DATA FRAME WRITTEN
– INIT HIGH, HDC HIGH, LDC LOW
– DOUT ACTIVE
YES
NO
NO
RESET,
INIT,
OR
PRGM
LOW
BIT
ERROR
YES
Initialization
Upon powerup, the device goes through an initialization
process. First, an internal power-on-reset circuit is trig-
gered when power is applied. Dedicated power pins
called V
DD
33 are used by the configuration logic. When
V
DD
33 reaches the voltage at which portions of the
FPGA begin to operate (2.0 V), the I/Os are configured
based on the configuration mode, as determined by the
mode select inputs M[2:0]. A time-out delay is initiated
when V
DD
33 reaches between 2.7 V to 3.0 V to allow
the power supply voltage to stabilize. The
INIT
and
DONE outputs are low. At powerup, if V
DD
33 does not
rise from 2.0 V to V
DD
33 in less than 25 ms, the user
should delay configuration by inputting a low into
INIT
,
PRGM
, or
RESET
until V
DD
33 is greater than the recom-
mended minimum operating voltage.
At the end of initialization, the default configuration
option is that the configuration RAM is written to a low
state. This prevents shorts prior to configuration. As a
configuration option, after the first configuration (i.e., at
reconfiguration), the user can reconfigure without
clearing the internal configuration RAM first. The
active-low, open-drain initialization signal
INIT
is
released and must be pulled high by an external resis-
tor when initialization is complete. To synchronize the
configuration of multiple FPGAs, one or more
INIT
pins
should be wire-ANDed. If
INIT
is held low by one or
more FPGAs or an external device, the FPGA remains
in the initialization state.
INIT
can be used to signal that
the FPGAs are not yet initialized. After
INIT
goes high
for two internal clock cycles, the mode lines (M[3:0])
are sampled, and the FPGA enters the configuration
state.
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