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Lucent Technologies Inc.
3
Preliminary Data Sheet
August 2000
ORCASeries 4 FPGAs
Figure
Figure 44. Slave Serial Configuration Schematic......70
Figure 45. Slave Parallel Configuration
Schematic ............................................................71
Figure 46. Daisy-Chain Configuration
Schematic ............................................................72
Page
Table
Table 22. Boundary-Scan Instructions .....................40
Table 23. Series 4E Boundary-Scan
Vendor-ID Codes..................................................41
Table 24. TAP Controller Input/Outputs....................43
Table 25. Readback Options ....................................46
Table 26. MPC 860 to ORCA MPI
Interconnection ....................................................48
Table 27. Embedded System Bus/MPI Registers.....50
Table 28. Interrupt Register Space Assignments.....50
Table 29. Status Register Space Assignments ........51
Table 30. Command Register Space
Assignments ........................................................51
Table 31. PPLL Specifications..................................52
Table 32. DPLL DS-1/E-1 Specifications..................53
Table 33. Dedicated Pin Per Package ......................53
Table 34. STS-3/STM-1 DPLL Specifications ..........54
Table 35. Phase-Lock Loops Index ..........................54
Table 36A. Configuration Frame Format
and Contents .......................................................61
Table 36B. Configuration Frame Format
and Contents for Embedded Block RAM .............61
Table 37. Configuration Frame Size .........................62
Table 38. Configuration Modes.................................63
Table 39. Absolute Maximum Ratings......................73
Table 40. Recommended Operating Conditions.......73
Table 41. Electrical Characteristics ..........................73
Table 42. Pin Descriptions........................................75
Table 43. ORCA I/Os Summary ...............................78
Table 44. OR4E6 352-Pin PBGA Pinout ..................79
Table 45. OR4E6 432-Pin EBGA Pinout ..................92
Table 46. OR4E6 680-Pin PBGAM Pinout ............. 106
Table 47. Series 4 Package Matrix......................... 131
Table 48. Package Options..................................... 131
Page
Table of Contents
(continued)
Table
Page
Table 1. ORCA Series 4—Available FPGA
Logic ...................................................................1
Table 2. System Performance ..................................5
Table 3. Look-Up Table Operating Modes ...............11
Table 4. Control Input Functionality .........................11
Table 5. Ripple Mode Equality Comparator
Functions and Outputs.........................................18
Table 6. SLIC Modes ...............................................22
Table 7. Configuration RAM Controlled Latch/
Flip-Flop Operation ..............................................25
Table 8. ORCA Series 4—Available Embedded
Block RAM ..........................................................27
Table 9. RAM Signals...............................................28
Table 10. FIFO Signals ............................................29
Table 11. Constant Multiplier Signals ......................30
Table 12. 8x8 Multiplier Signals ...............................30
Table 13. CAM Signals.............................................30
Table 14. Series 4 Programmable I/O
Standards.............................................................32
Table 15. PIO Options .............................................35
Table 16. PIO Register Control Signals ...................35
Table 17. PIO Logic Options.....................................36
Table 18. Compatible Mixed I/O Standards..............36
Table 19. LVDS I/O Specifications............................37
Table 20. LVDS Termination Pin ..............................37
Table 21. Dedicated Temperature Sensing ..............39