參數(shù)資料
型號： OR4E4
廠商： Lineage Power
英文描述： Field-Programmable Gate Arrays(現(xiàn)場可編程門陣列)
中文描述： 現(xiàn)場可編程門陣列（現(xiàn)場可編程門陣列）
文件頁數(shù)： 28/132頁
文件大小： 2667K
代理商： OR4E4
28
Lucent Technologies Inc.
Preliminary Data Sheet
August 2000
ORCA Series 4 FPGAs
Embedded Block RAM
(continued)
CAM Mode
The CAM block is a content address memory that pro-
vides fast address searches by receiving data input
and returning addresses that contain the data. Imple-
mented in each EBR are two 16-word x 8-bit CAM
function blocks.
The CAM has three modes: single match, multiple
match, and clear, which are all achieved in one clock
cycle. In single-match mode, an 8-bit data input is inter-
nally decoded and reports a match when data is
present in a particular RAM address. Its result is
reported by a corresponding single address bit. In mul-
tiple match, the same occurs with the exception of mul-
tiple address lines report the match. Clear mode is
used to clear the CAM contents in one clock cycle by
erasing all locations.)
Arbitration logic is optionally programmed by the user
to signal occurrences of data collisions as well as to
block both ports from writing at the same time. The
arbitration logic prioritizes PORT1. When utilizing the
arbiter, the signal BUSY indicates data is being written
to PORT1. This BUSY output signals PORT1 activity by
driving a high output. The arbitration default is enabled;
however, the user may disable the arbiter in configura-
tion. If the arbiter is turned off, both ports could be writ-
ten at the same time and the data would be corrupt. In
this scenario, the BUSY signal will indicate a possible
error.
There is also a user option which dedicates PORT 1 to
communications to the system bus. In this mode the
user logic only has access to PORT0 and arbitration
logic is enabled. The system bus utilizes the priority
given to it by the arbiter; therefore, the system bus will
always be able to write to the EBR.
Table 9. RAM Signals
Port Signals
I/O
Function
PORT 0
AR0[#:0]
AW0[#:0]
BW0<1:0>
I
I
I
Address to be read.
Address to be written.
Byte-write enable.
Byte = 8 bits + parity bit.
<1> = bits[17, 15:9] <0> = bits[16, 7:0]
Positive-edge asynchronous read clock.
Positive-edge synchronous write clock.
Enables read to output. Active-high.
Enables write to occur. Active-high.
Input data to be written to RAM.
Output data of memory contents at referenced address.
CKR0
CKW0
CSR0
CSW0
D [#:0]
Q [#:0]
I
I
I
I
I
O
PORT 1
AR1[#:0]
AW1[#:0]
BW1<1:0>
I
I
I
Address to be read.
Address to be written.
Byte-write enable.
Byte = 8 bits + parity bit.
<1> = bits[17, 15:9] <0> = bits[16, 7:0]
Positive-edge asynchronous read clock.
Positive-edge synchronous write clock.
Enables read to output. Active-high.
Enables write to occur. Active-high.
Input data to be written to RAM.
Output data of memory contents at referenced address.
CKR1
CKW1
CSR1
CSW1
D [#:0]
Q [#:0]
I
I
I
I
I
O
Control
BUSY
RESET
O
I
PORT1 writing. Active-high.
Data output registers cleared. Memory contents unaffected. Active-low.
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