參數(shù)資料
型號: OR4E4
廠商: Lineage Power
英文描述: Field-Programmable Gate Arrays(現(xiàn)場可編程門陣列)
中文描述: 現(xiàn)場可編程門陣列(現(xiàn)場可編程門陣列)
文件頁數(shù): 22/132頁
文件大?。?/td> 2667K
代理商: OR4E4
22
Lucent Technologies Inc.
Preliminary Data Sheet
August 2000
ORCA Series 4 FPGAs
Programmable Logic Cells
(continued)
As discussed in the memory mode section, if the SLIC
is placed into one of the modes where it contains both
buffers and a decode or AOI function (e.g.,
BUF_BUF_DEC mode), the DEC output can be gated
with the 3-state input signal. This allows up to a 6-input
decode (e.g., BUF_DEC_DEC mode) plus the 3-state
input to control the enable/disable of up to four buffers
per SLIC. Figure 15—Figure 19 show several configu-
rations of the SLIC, while Table 6 shows all of the possi-
ble modes.
Table 6. SLIC Modes
5-5744(F).a.
Figure 14. SLIC All Modes Diagram
Mode
No.
1
2
3
4
5
6
7
8
Mode
BUF
[3:0]
Buffer
Buffer
Buffer
Buffer
BUF
[7:4]
Buffer
Buffer
Decoder
Decoder Decoder
Buffer
Buffer
BUF
[9:8]
Buffer
Decoder
Buffer
BUFFER
BUF_BUF_DEC
BUF_DEC_BUF
BUF_DEC_DEC
DEC_BUF_BUF Decoder
DEC_BUF_DEC
Decoder
DEC_DEC_BUF
Decoder Decoder
DECODER
Decoder Decoder Decoder
Buffer
Decoder
Buffer
SIN9
I9
SOUT09
DEC
DEC
0/1
0/1
TRI
0/1
0/1
SOUT08
SOUT07
SOUT06
SOUT05
SOUT04
SOUT03
SOUT02
SOUT01
SOUT00
LOGIC 1 OR 0
SIN8
I8
LOGIC 1 OR 0
SIN7
I7
LOGIC 1 OR 0
SIN6
I6
LOGIC 1 OR 0
SIN5
I5
LOGIC 1 OR 0
SIN4
I4
LOGIC 1 OR 0
SIN3
I3
LOGIC 1 OR 0
SIN2
I2
LOGIC 1 OR 0
SIN1
I1
LOGIC 1 OR 0
SIN0
I0
LOGIC 1 OR 0
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