參數(shù)資料
型號： OR3TP12
英文描述： Field-Programmable System Chip (FPSC) Embedded Master/Target PCI Interface
中文描述： 現(xiàn)場可編程系統(tǒng)芯片（促進文化基金）嵌入式主/目標PCI接口
文件頁數(shù)： 82/128頁
文件大小： 2450K
代理商： OR3TP12
ORCAOR3TP12 FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
82
L Lucent Technologies Inc.
PCI Bus Core Target Controller Detailed Description
(continued)
Configuration Space of the PCI Bus Core
The following section describes the configuration space of the PCI bus core, as defined in the PCI Specification
and specific additions to this implementation. Note that the term configuration has two meanings: in the FPGA con-
text, it refers to the programming of the FPGA’s resources to define its functionality, and in the PCI context, it refers
to the process of initializing the personality of the PCI agent. Normally, this agent will reside at a unique location or
card slot defined by a physical address line
idsel
. The PCI’s configuration space is described as follows.
PCI Bus Core Configuration Space Organization
Table 24 shows the layout of the PCI bus core’s configuration space. The header type is 00 hex (non-PCI-to-PCI
bridge). All required features and many optional features are implemented. In this implementation, the defined con-
figuration space extends beyond 0x3F hex, and includes provisions for hot swap and FPGA configuration via the
PCI bus. Table 25 further details the content and function of each register in the PCI configuration space.
Table 24. Configuration Space Layout
31
Device ID
16 15
0
Vendor ID
00h
04h
08h
0Ch
10h
14h
18h
1Ch
20h
24h
28h
2Ch
30h
34h
3Ch
Status
Command
Class Code
Header Type
Revision ID
Cache Line Size
BIST
Latency Timer
Base Address Registers
Cardbus CIS Pointer
Subsystem ID
Subsystem Vendor ID
Expansion ROM Base Address
Reserved
Min_Gnt
Cap_Ptr
Interrupt Line
Max_Lat
Interrupt Pin
FPGA Configuration Command-Status Register 40h
FPGA Configuration Data Register
Scratch Register
Reserved
HS_CSR
Next Item
Reserved
44h
48c
40c
48h
54h
thru
FFh
Reserved
Capability ID
Reserved
相關PDF資料
PDF描述
OR62 OR62 is a 6-input OR gate with 2x drive strength
OR73 7-input OR gate with 3x drive strength.
OR8GU41 DIFFUSED TYPE (HIGH SPEED RECTIFIER APPLICATIONS)
ORCAORT4622 Field-Programmable System Chip (FPSC) Four-Channel x 622 Mbits/s Backplane Transceiver
ORCAORT82G5 1.0?.25/2.0?.5/3.125 Gbits/s Backplane Interface FPSC
相關代理商/技術參數(shù)
參數(shù)描述
OR3TP12-6BA256 制造商:未知廠家 制造商全稱:未知廠家 功能描述:User Programmable Special Function ASIC
OR3TP126BA256-DB 功能描述:FPGA - 現(xiàn)場可編程門陣列 2016 LUT 187 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
OR3TP12-6BA256I 制造商:未知廠家 制造商全稱:未知廠家 功能描述:User Programmable Special Function ASIC
OR3TP126BA256I-DB 功能描述:FPGA - 現(xiàn)場可編程門陣列 2016 LUT 187 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
OR3TP12-6BA352 制造商:未知廠家 制造商全稱:未知廠家 功能描述:User Programmable Special Function ASIC
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*