參數(shù)資料
型號： OR3TP12
英文描述： Field-Programmable System Chip (FPSC) Embedded Master/Target PCI Interface
中文描述： 現(xiàn)場可編程系統(tǒng)芯片（促進文化基金）嵌入式主/目標PCI接口
文件頁數(shù)： 12/128頁
文件大小： 2450K
代理商： OR3TP12
ORCAOR3TP12 FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
12
L Lucent Technologies Inc.
OR3TP12 Overview
(continued)
Independent data paths exist for the Master and Target FIFO interface. This allows for separate operation of Master
and Target functions, and the capability for a Master to transfer data to a Target on the same device.
In dual-port mode, the Master and Target FIFO interfaces share two unidirectional 32-bit data paths between the
FIFOs and the FPGA logic. This provides for full-rate transfers in 32-bit PCI bus operation, when operating the
FPGA application and PCI bus at the same frequency.
Quad-port mode provides two independent 16-bit data paths for each FIFO interface: one for read data and the
other for write data. This mode allows for simultaneous operations on either the Master or Target controller.
Diagrams for dual-port and quad-port operation are shown in Figure 2.
Embedded Core Options/FPGA Configuration
In addition to the Series 3 FPGA configuration modes, the OR3TP12 can also be configured via the PCI bus. Con-
figuration as discussed here covers two operations. There is configuration of the FPGA logic, and there is configu-
ration of the options available in the embedded core. Both are accomplished through the FPGA configuration
process. Readback of FPGA and PCI bus core options is also possible using the PCI bus or Series 3T FPGA read-
back modes. At powerup, the PCI bus core will be functional with a default PCI bus configuration space, as defined
in the PCI bus 2.1 specification, even prior to an initial configuration of the FPGA logic.
Figure 2. ORCA OR3TP12 PCI FPSC Block Diagram
5-6368.b
5-6368.a
QUAD-PORT MODE
DUAL-PORT MODE
73 USER I/O PADS
OR3T SERIES FPGA
14 ROWS x 18 COLUMNS
57
USER
I/O PADS
57
USER
I/O PADS
PCI
MASTER/TARGET
INTERFACE
PCI
BUS
DATA CONTROL
AND
MULTIPLEXING
32
32
16 DEEP
FIFO
64-bit x
16 DEEP
FIFO
64-bit x
32 DEEP
FIFO
64-bit x
32 DEEP
FIFO
64-bit x
73 USER I/O PADS
OR3T SERIES FPGA
14 ROWS x 18 COLUMNS
57
USER
I/O PADS
57
USER
I/O PADS
PCI
MASTER/TARGET
INTERFACE
PCI
BUS
DATA CONTROL
AND
MULTIPLEXING
16
16
16
16
16 DEEP
FIFO
64-bit x
16 DEEP
FIFO
64-bit x
32 DEEP
FIFO
64-bit x
32 DEEP
FIFO
64-bit x
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