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參數(shù)資料
| 型號： | OR3TP12 |
| 英文描述： | Field-Programmable System Chip (FPSC) Embedded Master/Target PCI Interface |
| 中文描述： | 現(xiàn)場可編程系統(tǒng)芯片（促進文化基金）嵌入式主/目標PCI接口 |
| 文件頁數(shù)： | 48/128頁 |
| 文件大?。?/td> | 2450K |
| 代理商： | OR3TP12 |
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48
Lucent Technologies Inc.
ORCAOR3TP12 FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
PCI Bus Core Master Controller
Detailed Description
(continued)
Example: Master Read, Burst Transaction
Figure 12 and Figure 13 show the timing of a four 32-bit
word Master burst read, on the dual-port FPGA inter-
face and quad-port FPGA interface, respectively. Oper-
ation is similar to that in the Master read, single-word
transaction, but extra data Dwords are requested by
the FPGA application. In Figure 12, the command/
address phase is initiated by the FPGA application
asserting Master address enable (
maenn
), while pro-
viding the Master command word and read burst length
on bus
datafmfpga
. Assuming, the Master will decode
a supplied burst length of two, and read byte enable
(MRDBEN[7:0] = 0x00), this is a burst operation. On
the next clock, the FPGA application provides the
32-bit address and ends the command/address phase
by asserting
mwlastcycn
.
ma_fulln
then will be
asserted, and the Master will begin negotiating for the
PCI bus.
To enter the dual-port read data phase,
maenn
is
deasserted,
mrdataenn
is asserted, and valid 32-bit
data words will be provided on bus
datatofpga
(
fifo_sel
= 0), providing the read data FIFO is not
empty (
mr_emptyn
= 1). For a burst transfer, the Mas-
ter FIFO interface will assert the signal
mrlastcycn
during the last clock of the data phase, and deasserted
otherwise. The completion of the data phase is indi-
cated by
mrlastcycn
asserted, requiring
mrdataenn
asserted, and the final data word.
For quad-port mode (Figure 13), the command/address
phase starts with the command and read burst length
transferring on the bus
mwdata
in sequential seg-
ments. The 18-bit Master command will be transferred
first on
mwdata
, followed the 18-bit read burst length,
with both validated by an asserted
maenn
. The 32-bit
address will be split into two 16-bit components with
the LSB being transferred first, also validated by an
asserted
maenn
. The command/address phase will
require four clock cycles, and
mwlastcycn
will be
asserted on the final or MSB component of the
address.
In the read data phase of the quad-port mode, the read
data will be transferred in 16-bit segments on bus
mrdata
. The read data phase will require two clock
cycles to transfer each 32-bit read data word across the
16-bit bus
mrdata
, providing
mrdataen
is asserted, the
read data FIFOs are not empty (
mr_emptyn
= 1).
mrlastcycn
will be deasserted for the all cycles of the
data phase, and asserted for final the 16-bit MSB com-
ponent.
Following this command/address setup, execution
begins on the PCI bus. Figure 14 shows the timing of a
typical transaction with a remote Target. The transac-
tion results in a normal completion. The remote Target
supports fast decode, and the protocol and timing are
as required by the PCI Specification.
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