參數(shù)資料
型號(hào)： OR3TP12
英文描述： Field-Programmable System Chip (FPSC) Embedded Master/Target PCI Interface
中文描述： 現(xiàn)場(chǎng)可編程系統(tǒng)芯片（促進(jìn)文化基金）嵌入式主/目標(biāo)PCI接口
文件頁(yè)數(shù)： 5/128頁(yè)
文件大?。?/td> 2450K
代理商： OR3TP12
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Lucent Technologies Inc.
Lucent Technologies Inc.
5
Data Sheet
March 2000
ORCA OR3TP12 FPSC
Embedded Master/Target PCI Interface
PCI Bus Core Highlights
(continued)
I
Operates at PCI bus speeds up to 66 MHz.
I
Comprises two independent controllers for Master
and Target.
I
Meets/exceeds all requirements for PICMG
*
Hot
Swap Friendly silicon, Full Hot Swap model, per the
CompactPCI
*
Hot Swap Specification, PICMG
2.1
R1.0.
I
PCI SIG Hot-Plug (R1.0) compliant.
I
Four internal FIFOs individually buffer both directions
of both the Master and Target interfaces:
— Both Master FIFOs are 64 bits wide by 32 bits
deep.
— Both Target FIFOs are 64 bits wide by 16 bits
deep.
I
Capable of no-wait-state, full-burst PCI transfers in
either direction, on either the Master or Target inter-
face. Dual 32-bit data paths extend into the FPGA
logic, permitting full-bandwidth, simultaneous bidirec-
tional data transfers of up to 264 Mbytes/s to be sus-
tained indefinitely.
I
Can be configured to provide either two 32-bit buses
(one in each direction) to be multiplexed between
Master and Target, or four independent 16-bit buses.
I
Provides many hardware options in the PCI bus core
that are set during FPGA logic configuration.
I
Operates within the requirements of the PCI 5 V and
3.3 V signaling environments, allowing the same
device to be used in 5 V or 3.3 V PCI systems.
I
FPGA is reconfigurable via the PCI interface configu-
ration space (as well as conventionally), allowing the
FPGA to be field-updated to meet late-breaking
requirements of emerging protocols.
I
Master:
— Generates all defined command codes except
interrupt acknowledge and special cycle.
— Capable of acting as the system's configuration
agent by booting up with the Master logic enabled.
— Provides multiple options to increase PCI bus
bandwidth.
I
Target:
— Responds legally to most command codes: inter-
rupt acknowledge, special cycle, and reserved
commands ignored; memory read multiple and
line handled as memory read; memory write and
invalidate handled as memory write.
— Implements Target abort, disconnect, retry, and
wait cycles.
— Handles delayed transactions.
— Handles fast back-to-back transactions.
— Supports programmable latency timer control.
— Method of handling wait-states is programmable
to allow tailoring to different Target data access
latencies.
— Decodes at medium speed.
I
Supports dual-address cycles (both as Master and
Target).
I
Supports all six base address registers (BARs), as
either memory (32-bit or 64-bit) or I/O. Any legal
page size can be independently specified for each
BAR during FPGA configuration.
I
Provides versatile clocking capabilities with FPGA
clocks sourced from PCI bus clock or elsewhere.
FIFO interface buffers asynchronous clock domains
between the PCI interface and FPGA-based logic.
I
PCI interface timing: meets or exceeds 33 MHz,
50 MHz, and 66 MHz PCI requirements.
I
Standard 256-byte PCI configuration space:
— Class code, revision ID.
— Latency timer.
— Cache line size.
— Subsystem ID.
— Subsystem vendor ID.
— Maximum latency, minimum grant.
— Interrupt line.
— Hot plug/hot swap capability.
* CompactPCIand PICMG are registered trademarks of the PCI
Industrial Computer Manufacturers Group.
Parameter
33 MHz
11.0 ns
7.0 ns
10.0 ns
2.0 ns
30.0 ns
50 MHz
7.5 ns
4.5 ns
6.5 ns
1.5 ns
20.0 ns
66 MHz
6.0 ns
3.0 ns
5.0 ns
1.0 ns
15.0 ns
Device clock = > out
Device setup time
Board prop. delay
Board clock skew
Total budget
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