參數(shù)資料
型號： OR3TP12
英文描述： Field-Programmable System Chip (FPSC) Embedded Master/Target PCI Interface
中文描述： 現(xiàn)場可編程系統(tǒng)芯片（促進(jìn)文化基金）嵌入式主/目標(biāo)PCI接口
文件頁數(shù)： 52/128頁
文件大小： 2450K
代理商： OR3TP12
ORCAOR3TP12 FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
52
L Lucent Technologies Inc.
PCI Bus Core Master Controller Detailed Description
(continued)
Table 16. Quad-Port Master Read, Duplicate Burst Length
1. When
maenn, mrdataenn,
and
ma_fulln
are deasserted high, the Master interface is idle.
2. When
maenn
is asserted low, a command/address phase is in progress.
3.
maenn
must be asserted low for command/address data to transfer and state to change.
4.
maenn
must be deasserted high and
mrdataenn
must be asserted low to execute the read data phase.
5. Next state = 0 if
mrlastcycn
is asserted low (end of Master read data phase).
6. Next state = 0 if
mwlastcycn
is asserted low (end of Master command/address phase).
Table 17. Quad-Port Master Read, Specified Burst Length
1. When
maenn, mrdataenn,
and
ma_fulln
are deasserted high, the Master interface is idle.
2. When
maenn
is asserted low, a command/address phase is in progress.
3.
maenn
must be asserted low for command/address data to transfer and state to change.
4.
maenn
must be deasserted high and
mrdataenn
must be asserted low to execute the read data phase.
5. Next state = 0 if
mrlastcycn
is asserted low (end of Master read data phase).
6. Next state = 0 if
mwlastcycn
is asserted low (end of Master command/address phase).
MStateCntr
Next State of
MStateCntr
Description
Data on Bus
mwdata[17:0]
Data on Bus
mrdata[15:0]
Notes
0
0
0
Idle
XX
2
XXXX
16
Command Word
—
1
1 or 0
Command Word
or Data[15:0]
Address[15:0] or
Data[31:16]
Address[31:16] or
Data[47:32]
Address[47:32] or
Data[63:48]
Address[63:48]
PCIData[15:0]
2, 3, 4, 5, 6
1
2 or 0
XX
2
, PCIAddress[15:0]
PCIData[15:0]
2, 3, 4, 5, 6
2
3 or 0
XX
2
, PCIAddress[15:0]
PCIData[47:32]
2, 3, 4, 5, 6
3
4 or 0
XX
2
, PCIAddress[47:32]
PCIData[63:48]
2, 3, 4, 5, 6
4
0
XX
2
, PCIAddress[63:48]
—
2, 3, 6
MStateCntr
Next State of
MStateCntr
0
1
Description
Data on Bus
mwdata[17:0]
XX
2
XXXX
16
Command Word
Data on Bus
mrdata[15:0]
—
PCIData[15:0]
Notes
0
0
Idle
1
Command Word
or Data[15:0]
Burst Length or
Data[31:16]
Address[15:0] or
Data[47:32]
Address[31:16] or
Data[63:48]
Address[47:32] or
Data[63:48]
Address[63:48]
2, 3, 4, 5, 6
1
2 or 0
Burst Length
PCIData[31:16]
2, 3, 4, 5, 6
2
3 or 0
XX
2
, PCIAddress[15:0]
PCIData[47:32]
2, 3, 4, 5, 6
3
4 or 0
XX
2
, PCIAddress[15:0]
PCIData[63:48]
2, 3, 4, 5, 6
4
5 or 0
XX
2
, PCIAd-
dress[47:32]
XX
2
, PCIAd-
dress[63:48]
—
2, 3, 6
5
0
—
2, 3, 6
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