
NT5TU256M4GE / NT5TU128M8GE / NT5TU64M16GG
1Gb DDR2 SDRAM
76
REV 1.0
06 / 2010
Timing Definition for Data Setup (tDS) and Hold Time (tDH)
VDDQ
VIH(ac) min
VIH(dc) min
VREF
VIL(dc) max
VIL(ac) max
VSS
t
DS
t
DH
t
DS
VREF
t
DH
DQS
Differential Input
Waveform
Single-ended Input
Waveform
1. Data input setup time with differential data strobe enabled MR[bit10]=0, is referenced from the input signal crossing at
the VIH(ac) level to the differential data strobe cross point for a rising signal, and from the input signal crossing at the VIL(ac)
level to differential data strobe cross point for a falling signal applied to the device under test. Input waveform timing with
single-ended data strobe enabled MR[bit10]=1, is referenced from the input signal crossing at the VIH(ac) level to the data
strobe crossing Vref for a rising signal, and from the input signal crossing at the VIL(ac) level to the single-ended data
strobe crossing Vref for a falling signal applied to the device under test.
2. Data input hold time with differential data strobe enabled MR[bit10]=0, is referenced from the input signal crossing at the
VIL(dc) level to the differential data strobe cross point for a rising signal and VIH(dc) to the differential data strobe cross
point for a falling signal applied to the device under test. Input waveform timing with single-ended data strobe enabled
MR[bit10]=1, is referenced from the input signal crossing at the VIL(dc) level to the single-ended data strobe crossing Vref
for a rising signal and VIH(dc) to the single-ended data strobe crossing Vref for a falling signal applied to the device under
test.