參數(shù)資料
型號: NT5TU64M16DG-3C
廠商: NANYA TECHNOLOGY CORP
元件分類: DRAM
英文描述: 64M X 16 DDR DRAM, 0.45 ns, PBGA84
封裝: GREEN, BGA-84
文件頁數(shù): 74/85頁
文件大?。?/td> 2622K
代理商: NT5TU64M16DG-3C
NT5TU256M4GE / NT5TU128M8GE / NT5TU64M16GG
1Gb DDR2 SDRAM
76
REV 1.0
06 / 2010
Timing Definition for Data Setup (tDS) and Hold Time (tDH)
VDDQ
VIH(ac) min
VIH(dc) min
VREF
VIL(dc) max
VIL(ac) max
VSS
t
DS
t
DH
t
DS
VREF
t
DH
DQS
Differential Input
Waveform
Single-ended Input
Waveform
1. Data input setup time with differential data strobe enabled MR[bit10]=0, is referenced from the input signal crossing at
the VIH(ac) level to the differential data strobe cross point for a rising signal, and from the input signal crossing at the VIL(ac)
level to differential data strobe cross point for a falling signal applied to the device under test. Input waveform timing with
single-ended data strobe enabled MR[bit10]=1, is referenced from the input signal crossing at the VIH(ac) level to the data
strobe crossing Vref for a rising signal, and from the input signal crossing at the VIL(ac) level to the single-ended data
strobe crossing Vref for a falling signal applied to the device under test.
2. Data input hold time with differential data strobe enabled MR[bit10]=0, is referenced from the input signal crossing at the
VIL(dc) level to the differential data strobe cross point for a rising signal and VIH(dc) to the differential data strobe cross
point for a falling signal applied to the device under test. Input waveform timing with single-ended data strobe enabled
MR[bit10]=1, is referenced from the input signal crossing at the VIL(dc) level to the single-ended data strobe crossing Vref
for a rising signal and VIH(dc) to the single-ended data strobe crossing Vref for a falling signal applied to the device under
test.
相關(guān)PDF資料
PDF描述
NTA2425E
NTA2425F
NTA2410-10
NTD2410F
NTA2425-10
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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