參數(shù)資料
型號(hào)： NT5TU64M16DG-3C
廠商： NANYA TECHNOLOGY CORP
元件分類： DRAM
英文描述： 64M X 16 DDR DRAM, 0.45 ns, PBGA84
封裝： GREEN, BGA-84
文件頁(yè)數(shù)： 35/85頁(yè)
文件大?。?/td> 2622K
代理商： NT5TU64M16DG-3C
NT5TU256M4GE / NT5TU128M8GE / NT5TU64M16GG
1Gb DDR2 SDRAM
40
REV 1.0
06 / 2010
Burst Write followed by Precharge
Minimum Write to Precharge command spacing to the same bank = WL + BL/2 + tWR. For write cycles, a delay
must be satisfied from the completion of the last burst write cycle until the Precharge command can be issued.
This delay is known as a write recovery time (tWR) referenced from the completion of the burst write to the
Precharge command. No Precharge command should be issued prior to the tWR delay, as DDR2 SDRAM does
not support any burst interrupt by a Precharge command. tWR is an analog timing parameter (see the AC table
in this datasheet) and is not the programmed value for tWR in the MRS.
Examples:
Burst Write followed by Precharge : WL = (RL - 1) = 3, BL = 4, tWR = 3
NOP
WRITE A
Post CAS
T
0
T
2
T
1
T
3
T
4
T
5
T
6
T
7
T
8
WL = 3
BW-P3
CMD
DQ
NOP
DIN
A0
DIN
A1
DIN
A2
DIN
A3
>=tWR
Completion of
the Burst Write
Precharge
A
NOP
DQS,
DQS
CK, CK
Burst Write followed by Precharge : WL = (RL - 1) = 4, BL = 4, tWR = 3
NOP
WRITE A
Post CAS
T0
T2
T1
T3
T4
T5
T6
T7
T9
WL = 4
BW-P4
CMD
DQ
NOP
DIN A0 DIN A1 DIN A2 DIN A3
tWR
Completion of
the Burst Write
Precharge
A
NOP
DQS,
DQS
CK, CK
相關(guān)PDF資料
PDF描述
NTA2425E
NTA2425F
NTA2410-10
NTD2410F
NTA2425-10
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