參數(shù)資料
型號: NT5TU64M16DG-3C
廠商: NANYA TECHNOLOGY CORP
元件分類: DRAM
英文描述: 64M X 16 DDR DRAM, 0.45 ns, PBGA84
封裝: GREEN, BGA-84
文件頁數(shù): 68/85頁
文件大小: 2622K
代理商: NT5TU64M16DG-3C
NT5TU256M4GE / NT5TU128M8GE / NT5TU64M16GG
1Gb DDR2 SDRAM
70
REV 1.0
06 / 2010
Electrical Characteristics & AC Timing - Absolute Specification
Timing Parameter by Speed Grade
(VDDQ = 1.8V ± 0.1V; VDD = 1.8V ± 0.1V)
Symbol
Parameter
DDR2-667
DDR2-800
Units
Min.
Max.
Min.
Max.
tCK(avg)
Clock cycle time, CL=x, (Average)
3000
8000
2500
8000
ps
tCH(avg)
CK,
high-level width (Average)
0.48
0.52
0.48
0.52
tCK(avg)
tCL(avg)
CK,
low-level width (Average)
0.48
0.52
0.48
0.52
tCK(avg)
WL
Write command to DQS associated clock edge
RL-1
nCK
tDQSS
DQS latching rising transitions to associated clock edges
-0.25
0.25
-0.25
0.25
tCK(avg)
tDSS
DQS falling edge to CK setup time
0.2
-
0.2
-
tCK(avg)
tDSH
DQS falling edge hold time from CK
0.2
-
0.2
-
tCK(avg)
tDQSL,H
DQS input low (high) pulse width
0.35
-
0.35
-
tCK(avg)
tWPRE
Write preamble
0.35
-
0.35
-
tCK(avg)
tWPST
Write postamble
0.4
0.6
0.4
0.6
tCK(avg)
tIS
Address and control input setup time
200
-
175
-
ps
tIH
Address and control input hold time
275
-
250
-
ps
tIPW
Address and control input pulse width (each input)
0.6
-
0.6
-
tCK(avg)
tDS
DQ and DM input setup time
differential
100
-
50
-
ps
tDH
DQ and DM input hold time
differential
175
-
125
-
ps
相關(guān)PDF資料
PDF描述
NTA2425E
NTA2425F
NTA2410-10
NTD2410F
NTA2425-10
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