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參數(shù)資料
| 型號： | NT5TU64M16DG-3C |
| 廠商： | NANYA TECHNOLOGY CORP |
| 元件分類： | DRAM |
| 英文描述： | 64M X 16 DDR DRAM, 0.45 ns, PBGA84 |
| 封裝： | GREEN, BGA-84 |
| 文件頁數(shù)： | 43/85頁 |
| 文件大?。?/td> | 2622K |
| 代理商： | NT5TU64M16DG-3C |
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NT5TU256M4GE / NT5TU128M8GE / NT5TU64M16GG
1Gb DDR2 SDRAM
48
REV 1.0
06 / 2010
Power-Down
Power-down is synchronously entered when CKE is registered low, along with NOP or Deselect command. CKE is not
allowed to go low while mode register or extended mode register command time, or read or write operation is in progress.
CKE is allowed to go low while any other operation such as row activation, Precharge, Auto-Precharge or Auto-Refresh is
in progress, but power-down IDD specification will not be applied until finishing those operations.
The DLL should be in a locked state when power-down is entered. Otherwise DLL should be reset after exiting power-down
mode for proper read operation.
If power-down occurs when all banks are precharged, this mode is referred to as Precharge Power-down; if power-down
occurs when there is a row active in any bank, this mode is referred to as Active Power-down. For Active Power-down two
different power saving modes can
be selected within the MRS register, address bit A12. When A12 is set to “l(fā)ow” this mode
is referred as “standard active power-down mode” and a fast power-down exit timing defined by the tXARD timing parameter
can be used. When A12 is set to “high” this mode is referred as a power saving “l(fā)ow power active power-down mode”. This
mode takes longer to exit from the power-down mode and the tXARDS timing parameter has to be satisfied.
Entering power-down deactivates the input and output buffers, excluding CK, CK, ODT and CKE. Also the DLL is disabled
upon entering Precharge Power-down or slow exit active power-down, but the DLL is kept enabled during fast exit active
power-down.
In power-down mode, CKE low and a stable clock signal must be maintained at the inputs of the DDR2
SDRAM, and all other input signals are “Dont Care”. Power-down duration is limited by 9 times tREFI of the device.
The power-down state is synchronously exited when CKE is registered high (along with a NOP or Deselect command). A
valid, executable command can be applied with power-down exit latency, tXP, tXARD or tXARDS, after CKE goes high.
Power-down exit latencies are defined in the AC spec table of this data sheet.
Power-Down Entry
Active Power-down mode can be entered after an activate command. Precharge Power-down mode can be entered after a
precharge, Precharge-All or internal precharge command. It is also allowed to enter power-mode after an Auto-Refresh
command or
MRS / EMRS(1) command when tMRD is satisfied.
Active Power-down mode entry is prohibited as long as a Read Burst is in progress, meaning CKE should be kept high until
the burst operation is finished. Therefore Active Power-Down mode entry after a Read or Read with Auto-Precharge
command is allowed after RL + BL/2 is satisfied.
Active Power-down mode entry is prohibited as long as a Write Burst and the internal write recovery is in progress. In case
of a write command, active power-down mode entry is allowed then WL + BL/2 + tWTR is satisfied.
In case of a write command with Auto-Precharge, Power-down mode entry is allowed after the internal precharge command
has been executed, which WL + BL/2 + WR is starting from the write with Auto-Precharge command. In case the DDR2
SDRAM enters the Precharge Power-down mode.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| NT5TU64M16GG-AC | 制造商:Nanya Technology Corporation 功能描述:DRAM |
| NT5TU64M16GG-ACI | 制造商:Nanya Technology Corporation 功能描述:DRAM |
| NT5TU64M16HG-AC | 制造商:Nanya Technology Corporation 功能描述:MEMORY IC |
| NT5TU64M16HG-BE | 制造商:Nanya Technology Corporation 功能描述:MEMORY IC |
| NT6 | 功能描述:烙鐵 Weller Chisel Tip For WMP Solder Penc RoHS:否 制造商:Weller 產(chǎn)品:Soldering Stations 類型:Digital, Iron, Stand, Cleaner 瓦特:50 W 最大溫度:+ 850 F 電纜類型:US Cord Included |
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