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參數(shù)資料
| 型號： | NT5TU64M16DG-3C |
| 廠商： | NANYA TECHNOLOGY CORP |
| 元件分類： | DRAM |
| 英文描述： | 64M X 16 DDR DRAM, 0.45 ns, PBGA84 |
| 封裝： | GREEN, BGA-84 |
| 文件頁數(shù)： | 56/85頁 |
| 文件大小： | 2622K |
| 代理商： | NT5TU64M16DG-3C |
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NT5TU256M4GE / NT5TU128M8GE / NT5TU64M16GG
1Gb DDR2 SDRAM
6
REV 1.0
06 / 2010
Input / Output Functional Description
Symbol
Type
Function
CK,
Input
Clock: CK and
are differential clock inputs. All address and control input signals are sampled
on the crossing of the positive edge of CK and negative edge of
. Output (read) data is
referenced to the crossings of CK and
(both directions of crossing).
CKE
Input
Clock Enable: CKE high activates, and CKE low deactivates, internal clock signals and device
input buffers and output drivers. Taking CKE low provides Precharge Power-Down and
Self-Refresh operation (all banks idle), or Active Power-Down (row Active in any bank). CKE is
synchronous for power down entry and exit and for Self-Refresh entry. CKE is asynchronous for
Self-Refresh exit. After VREF has become stable during the power on and initialization sequence, it
must be maintained for proper operation of the CKE receiver. For proper self-refresh entry and
exit, VREF must maintain to this input. CKE must be maintained high throughout read and write
accesses. Input buffers, excluding CK,
, ODT and CKE are disabled during Power Down. Input
buffers, excluding CKE, are disabled during Self-Refresh.
Input
Chip Select: All commands are masked when
is registered high. provides for external rank
selection on systems with multiple memory ranks.
is considered part of the command code.
, ,
Input
Command Inputs:
, and (along with ) define the command being entered.
DM, LDM, UDM
Input
Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is
sampled high coincident with that input data during a Write access. DM is sampled on both edges
of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS loading. For
x8 device, the function of DM or RDQS /
is enabled by EMRS command.
BA0 - BA2
Input
Bank Address Inputs: BA0, BA1, and BA2 define to which bank an Active, Read, Write or
Precharge command is being applied. Bank address also determines if the mode register or
extended mode register is to be accessed during a MRS or EMRS cycle.
A0
– A13
Input
Address Inputs: Provides the row address for Activate commands and the column address and
Auto Precharge or Read/Write commands to select one location out of the memory array in the
respective bank. A10 is sampled during a Precharge command to determine whether the
precharge applies to one bank (A10=low) or all banks (A10=high). If only one bank is to be
precharged, the bank is selected by BA0-BA2. The address inputs also provide the op-code during
Mode Register Set commands.A13 Row address use on x8 components only.
DQ
Input/output
Data Inputs/Output: Bi-directional data bus.
DQS, (
)
LDQS, (
),
UDQS,(
)
Input/output
Data Strobe: output with read data, input with write data.
Edge aligned with read data, centered
with write data. For the x16, LDQS corresponds to the data on DQ0 - DQ7; UDQS corresponds to
the data on DQ8-DQ15. The data strobes DQS, LDQS, UDQS, and RDQS may be used in single
ended mode or paired with the optional complementary signals
, , to provide
differential pair signaling to the system during both reads and writes. An EMRS(1) control bit
enables or disables the complementary data strobe signals.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| NT5TU64M16GG-AC | 制造商:Nanya Technology Corporation 功能描述:DRAM |
| NT5TU64M16GG-ACI | 制造商:Nanya Technology Corporation 功能描述:DRAM |
| NT5TU64M16HG-AC | 制造商:Nanya Technology Corporation 功能描述:MEMORY IC |
| NT5TU64M16HG-BE | 制造商:Nanya Technology Corporation 功能描述:MEMORY IC |
| NT6 | 功能描述:烙鐵 Weller Chisel Tip For WMP Solder Penc RoHS:否 制造商:Weller 產(chǎn)品:Soldering Stations 類型:Digital, Iron, Stand, Cleaner 瓦特:50 W 最大溫度:+ 850 F 電纜類型:US Cord Included |
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