參數(shù)資料
型號(hào): NT5TU64M16DG-3C
廠商: NANYA TECHNOLOGY CORP
元件分類(lèi): DRAM
英文描述: 64M X 16 DDR DRAM, 0.45 ns, PBGA84
封裝: GREEN, BGA-84
文件頁(yè)數(shù): 72/85頁(yè)
文件大?。?/td> 2622K
代理商: NT5TU64M16DG-3C
NT5TU256M4GE / NT5TU128M8GE / NT5TU64M16GG
1Gb DDR2 SDRAM
74
REV 1.0
06 / 2010
Reference Loads, Setup & Hold Timing Definition and Slew Rate Derating
Reference Load for Timing Measurements
The figure represents the timing reference load used in defining the relevant timing parameters of the device. It is not
intended to either a precise representation of the typical system environment or a depiction of the actual load presented by
a production tester. System designers should use IBIS or other simulation tools to correlate the timing reference load to a
system environment. Manufacturers correlate to their production test conditions, generally a coaxial transmission line
terminated at the tester electronics. This reference load is also used for output slew rate characterization.
25 Ohm
Vtt = VDDQ / 2
CK, CK
DUT
Timing Reference Points
VDDQ
DQ
DQS
RDQS
The output timing reference voltage level for single ended signals is the cross point with VTT.
The output timing reference voltage level for differential signals is the cross point of the true (e.g. DQS) and the
complement (e.g.
) signal.
相關(guān)PDF資料
PDF描述
NTA2425E
NTA2425F
NTA2410-10
NTD2410F
NTA2425-10
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