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參數(shù)資料
| 型號： | NAND99R3M2AZBB5E |
| 廠商： | NUMONYX |
| 元件分類： | 存儲器 |
| 英文描述： | SPECIALTY MEMORY CIRCUIT, PBGA107 |
| 封裝： | 10.50 X 13 MM, 1.20 MM HEIGHT, 0.80 MM PITCH, ROHS COMPLIANT, TFBGA-107 |
| 文件頁數(shù)： | 11/33頁 |
| 文件大小： | 724K |
| 代理商： | NAND99R3M2AZBB5E |
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NANDxxxxMx
Signals description
19/32
2.18
LPSDRAM Write Enable (WD)
The Write Enable input, WD, controls writing.
2.19
LPSDRAM Clock Input (K)
The Clock signal, K, is used to clock the read and write cycles. During normal operation, the
Clock Enable pin, KE, is High, VIH. The Clock signal K can be suspended to switch the
device to the self-refresh, power-down or deep power-down mode by driving KE Low, VIL.
2.20
LPSDRAM Clock Input (K)
The Clock signal, K, is only available on the DDR LPSDRAM and is used in conjunction with
the Clock signal, K.
All LPSDRAM input signals except DQM0/DQM1/DQM2/DQM3, UDQS/LDQS and DQ0-
DQ31 are referred to the crosspoint of K rising edge and K falling edge.
2.21
LPSDRAM Clock Enable (KE)
The Clock Enable, KE, pin is used to control the synchronization of the signals with Clock
signal K. If KE is High, VIH, the next Clock rising edge is valid. When KE is Low, VIL, the
signals are no longer clocked and data read and write cycles are extended. KE is also
involved in switching the device to the self-refresh, power-down and deep power-down
modes.
2.22
Lower/Upper Data Read/Write Strobe input/output (LDQS,
UDQS)
LDQS and UDQS can be either input or output signals, and act as Write Data Strobe and
Read Data Strobe respectively. LDQS and UDQS are the strobe signals for DQ0 to DQ7 and
DQ8 to DQ15, respectively.
2.23
LPSDRAM data input/output mask pins (DQM0, DQM1,
DQM2, DQM3)
DQM2 and DQM3 are available only in the NAND99W3M1 and NANDA9W3M1, where the
bus width is ×32. The data input/output mask pins are input signals used to mask the read or
write data. The DQM latency is two clock cycles for read operations and there is no latency
for write operations.
2.24
LPSDRAM VDDD supply voltage
VDDD provides the power supply to the internal core of the memory device. It is the main
power supply for all read and write operations.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| NAND99R3M2AZBB5F | 制造商:Micron Technology Inc 功能描述:WIRELESS - Tape and Reel |
| NAND99R3M4BZBB5E | 制造商:Micron Technology Inc 功能描述:WIRELESS - Trays |
| NAND99R3M4BZBB5F | 制造商:Micron Technology Inc 功能描述:WIRELESS - Tape and Reel |
| NAND99R4M2AZBA5E | 制造商:Micron Technology Inc 功能描述:WIRELESS - Trays |
| NAND99R4M4BZBA5E | 制造商:Micron Technology Inc 功能描述:WIRELESS - Trays |
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