參數(shù)資料
型號(hào)： MT28F640J3
廠商： Micron Technology, Inc.
英文描述： 64Mb Flash Memory(64Mb閃速存儲(chǔ)器)
中文描述： 64MB Flash記憶體（64兆閃速存儲(chǔ)器）
文件頁(yè)數(shù)： 23/45頁(yè)
文件大?。?/td> 317K
代理商： MT28F640J3
23
64Mb, 32Mb SirusFlash Memory
MT28F640J3_2.p65 – Rev. 1, Pub. 12/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
64Mb, 32Mb
SIRUSFLASH MEMORY
PRELIMINARY
CLEAR BLOCK LOCK BITS COMMAND
The CLEAR BLOCK LOCK BITS command can clear
all set block lock bits in parallel. This command is in-
valid when the ISM is running or the device is sus-
pended. The CLEAR BLOCK LOCK BITS command is
executed by a two-cycle sequence. First, a clear block
lock bits setup is written, followed by a CLEAR BLOCK
LOCK BITS CONFIRM command. Then the device au-
tomatically outputs status register data when read (see
Figure 9). The CPU can detect completion of the clear
block lock bits event by analyzing the STS pin output or
the status register bit SR7. When the operation is com-
pleted, status register bit SR5 should be checked. If a
clear block lock bits error is detected, the status register
should be cleared. The CEL remains in read status reg-
ister mode until another command is issued.
This two-step setup sequence ensures that block
lock bits are not accidentally cleared. An invalid clear
block lock bits command sequence results in status
register bits SR4 and SR5 being set to “1.” Also, a reli-
able CLEAR BLOCK LOCK BITS operation can only oc-
cur when V
CC
and V
PEN
are valid. If a CLEAR BLOCK
LOCK BITS operation is attempted when V
PEN
≤
V
PENLK
,
SR3 and SR5 are set to “1.” If a CLEAR BLOCK LOCK
BITS operation is aborted due to V
PEN
or V
CC
transitioning
out of valid range, block lock bit values are left in an
undetermined state. To initialize block lock bit con-
tents to known values, a repeat of CLEAR BLOCK LOCK
BITS is required.
PROTECTION REGISTER PROGRAM
COMMAND
The 3V SirusFlash memory includes a 128-bit pro-
tection register to increase the security of a system
design. For example, the number contained in the pro-
tection register can be used for the Flash component to
communicate with other system components, such as
the CPU or ASIC, to prevent device substitution. The
128 bits of the protection register are divided into two
64-bit segments. One of the segments is programmed
at the Micron factory with a unique and unchangeable
64-bit number. The other segment is left blank for cus-
tomers to program as needed. After the customer seg-
ment is programmed, it can be locked to prevent repro-
gramming.
READING THE PROTECTION REGISTER
The protection register is read in the identification
read mode. The device is switched to identification
read mode by writing the READ IDENTIFIER command
(90h). When in this mode, READ cycles from addresses
shown in Table 18 or Table 19 retrieve the specified
information. To return to read array mode, the READ
ARRAY command (FFh) must be written.
PROGRAMMING THE PROTECTION REGISTER
The protection register bits are programmed with
two-cycle PROTECTION PROGRAM commands.
The 64-bit number is programmed 16 bits at a time
for word-wide parts and eight bits at a time for byte-
wide parts. First, the PROTECTION PROGRAM SETUP
command, C0h, is written. The next write to the device
latches in addresses and data, and programs the speci-
fied location. The allowable addresses are shown
in Table 18 and Table 19. Any attempt to address PRO-
TECTION PROGRAM commands outside the defined
protection register address space results in a status
register error (program error bit SR4 is set to “1”). At-
tempting to program a locked protection register seg-
ment results in a status register error (program error bit
SR4 and lock error bit SR1 are set to “1”).
LOCKING THE PROTECTION REGISTER
By programming bit 1 of the PR-LOCK location to
“0,” the user-programmable segment of the protection
register is lockable. To protect the unique device num-
ber, bit 0 of this location is programmed to “0” at the
Micron factory. Bit 1 is set using the PROTECTION PRO-
GRAM command to program “FFFDh” to the PR-LOCK
location. When these bits have been programmed, no
further changes can be made to the values stored in
the protection register. PROTECTION PROGRAM com-
mands to a locked section will result in a status register
error (program error bit SR4 and lock error bit SR1 are
set to “1”). Note that the protection register lockout
state is not reversible.
Figure 3
Protection Register Memory Map
NOTE:
A0 is not used in x16 mode when accessing the
protection register map (see Table 18 for x16
addressing). A0 is used for x8 mode (see Table 19 for
x8 addressing).
4 Words
Factory-Programmed
4 Words
User-Programmed
1 Word Lock
88h
85h
84h
81h
80h
Word
Address
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參數(shù)描述
MT28F640J3BS-115 ET 功能描述:IC FLASH 64MBIT 115NS 64FBGA RoHS:是 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:SDRAM 存儲(chǔ)容量:256M（8Mx32） 速度:143MHz 接口:并聯(lián) 電源電壓:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:90-VFBGA 供應(yīng)商設(shè)備封裝:90-VFBGA（8x13） 包裝:托盤 其它名稱:Q2841869
MT28F640J3BS-115 ET TR 功能描述:IC FLASH 64MBIT 115NS 64FBGA RoHS:是 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:378 系列:- 格式 - 存儲(chǔ)器:閃存 存儲(chǔ)器類型:FLASH 存儲(chǔ)容量:8M（1M x 8，512K x 16） 速度:110ns 接口:并聯(lián) 電源電壓:2.7 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-CBGA 供應(yīng)商設(shè)備封裝:48-CBGA（7x7） 包裝:托盤
MT28F640J3BS-115 GMET 功能描述:IC FLASH 64MBIT 115NS 64FBGA RoHS:是 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:SDRAM 存儲(chǔ)容量:256M（8Mx32） 速度:143MHz 接口:并聯(lián) 電源電壓:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:90-VFBGA 供應(yīng)商設(shè)備封裝:90-VFBGA（8x13） 包裝:托盤 其它名稱:Q2841869
MT28F640J3BS-115 GMET TR 功能描述:IC FLASH 64MBIT 115NS 64FBGA RoHS:是 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:378 系列:- 格式 - 存儲(chǔ)器:閃存 存儲(chǔ)器類型:FLASH 存儲(chǔ)容量:8M（1M x 8，512K x 16） 速度:110ns 接口:并聯(lián) 電源電壓:2.7 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-CBGA 供應(yīng)商設(shè)備封裝:48-CBGA（7x7） 包裝:托盤
MT28F640J3BS-115 MET 功能描述:IC FLASH 64MBIT 115NS 64FBGA RoHS:是 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:SDRAM 存儲(chǔ)容量:256M（8Mx32） 速度:143MHz 接口:并聯(lián) 電源電壓:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:90-VFBGA 供應(yīng)商設(shè)備封裝:90-VFBGA（8x13） 包裝:托盤 其它名稱:Q2841869
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