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參數(shù)資料
| 型號： | MT28F640J3 |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | 64Mb Flash Memory(64Mb閃速存儲器) |
| 中文描述： | 64MB Flash記憶體（64兆閃速存儲器） |
| 文件頁數(shù)： | 19/45頁 |
| 文件大?。?/td> | 317K |
| 代理商： | MT28F640J3 |
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19
64Mb, 32Mb SirusFlash Memory
MT28F640J3_2.p65 – Rev. 1, Pub. 12/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
64Mb, 32Mb
SIRUSFLASH MEMORY
PRELIMINARY
Table 16
Extended Status Register Definitions (XSR)
WBS
7
RESERVED
6–0
CLEAR STATUS REGISTER COMMAND
The ISM sets the status register bits SR5, SR4, SR3,
and SR1 to “1s.” These bits, which indicate various
failure conditions, can only be reset by the CLEAR STA-
TUS REGISTER command. Allowing system software to
reset these bits can perform several operations (such
as cumulatively erasing or locking multiple blocks or
writing several bytes in sequence). To determine if an
error occurred during the sequence, the status register
may be polled. To clear the status register, the CLEAR
STATUS REGISTER command (50h) is written. The
CLEAR STATUS REGISTER command functions inde-
pendently of the applied V
PEN
voltage and is only valid
when the ISM is off or the device is suspended.
BLOCK ERASE COMMAND
The BLOCK ERASE command is a two-cycle com-
mand that erases one block. First, a block erase setup is
written, followed by a block erase confirm. This com-
mand sequence requires an appropriate address within
the block to be erased. The ISM handles all block pre-
conditioning, erase, and verify. Time
t
WB after the two-
cycle block erase sequence is written, the device auto-
matically outputs status register data when read. The
CPU can detect block erase completion by analyzing
the output of the STS pin or status register bit SR7.
Toggle OE# or CEx to update the status register. Upon
block erase completion, status register bit SR5 should
be checked to detect any block erase error. When an
error is detected, the status register should be cleared
before system software attempts corrective actions.
The CEL remains in read status register mode until a
new command is issued. This two-step setup command
sequence ensures that block contents are not acciden-
tally erased. An invalid block erase command sequence
results in status register bits SR4 and SR5 being set to
“1.” Also, reliable block erasure can only occur when
V
CC
is valid and V
PEN
= V
PENH
. Note that SR3 and SR5 are
set to “1” if block erase is attempted while V
PEN
≤
V
PENLK
.
Successful block erase requires that the corresponding
block lock bit be cleared. Similarly, SR1 and SR5 are set
to “1” if block erase is attempted when the correspond-
ing block lock bit is set.
BLOCK ERASE SUSPEND COMMAND
The BLOCK ERASE SUSPEND command allows
block erase interruption in order to read or program
data in another block of memory. Writing the BLOCK
ERASE SUSPEND command immediately after start-
ing the block erase process requests that the ISM sus-
pend the block erase sequence at an appropriate point
in the algorithm. When reading after the BLOCK ERASE
SUSPEND command is written, the device outputs sta-
tus register data. Polling status register bit SR7, fol-
lowed by SR6, shows when the BLOCK ERASE opera-
tion has been suspended. In the default mode, STS
also transitions to V
OH
.
t
LES defines the block erase
suspend latency. At this point, a READ ARRAY com-
mand can be written to read data from blocks other
than that which is suspended. During erase suspend
to program data in other blocks, a program command
sequence can also be issued. During a PROGRAM op-
eration with block erase suspended, status register bit
SR7 returns to “0” and STS output (in default mode)
transitions to V
OL
. However, SR6 remains “1” to indicate
block erase suspend status. Using the PROGRAM SUS-
PEND command, a PROGRAM operation can also be
suspended. Resuming a suspended programming op-
eration by issuing the PROGRAM RESUME command
HIGH-Z
WHEN
BUSY
No
STATUS REGISTER BITS
NOTES
XSR7 = WRITE BUFFER STATUS (WBS)
1 = Write Buffer Available
0 = Write Buffer Not Available
After a BUFFER WRITE command,
XSR7 = 1 indicates that a write buffer is
available. SR6–SR0 are reserved for
future use and should be masked when
polling the status register.
Y es
XSR6–XSR0 = RESERVED FOR FUTURE
ENHANCEMENTS
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| MT28F640J3BS-115 ET | 功能描述:IC FLASH 64MBIT 115NS 64FBGA RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:1 系列:- 格式 - 存儲器:RAM 存儲器類型:SDRAM 存儲容量:256M（8Mx32） 速度:143MHz 接口:并聯(lián) 電源電壓:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:90-VFBGA 供應商設(shè)備封裝:90-VFBGA（8x13） 包裝:托盤 其它名稱:Q2841869 |
| MT28F640J3BS-115 ET TR | 功能描述:IC FLASH 64MBIT 115NS 64FBGA RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:378 系列:- 格式 - 存儲器:閃存 存儲器類型:FLASH 存儲容量:8M（1M x 8，512K x 16） 速度:110ns 接口:并聯(lián) 電源電壓:2.7 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-CBGA 供應商設(shè)備封裝:48-CBGA（7x7） 包裝:托盤 |
| MT28F640J3BS-115 GMET | 功能描述:IC FLASH 64MBIT 115NS 64FBGA RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:1 系列:- 格式 - 存儲器:RAM 存儲器類型:SDRAM 存儲容量:256M（8Mx32） 速度:143MHz 接口:并聯(lián) 電源電壓:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:90-VFBGA 供應商設(shè)備封裝:90-VFBGA（8x13） 包裝:托盤 其它名稱:Q2841869 |
| MT28F640J3BS-115 GMET TR | 功能描述:IC FLASH 64MBIT 115NS 64FBGA RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:378 系列:- 格式 - 存儲器:閃存 存儲器類型:FLASH 存儲容量:8M（1M x 8，512K x 16） 速度:110ns 接口:并聯(lián) 電源電壓:2.7 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-CBGA 供應商設(shè)備封裝:48-CBGA（7x7） 包裝:托盤 |
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