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參數(shù)資料
| 型號： | MR83C154XXX-30/883 |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 30 MHz, MICROCONTROLLER, CQCC44 |
| 封裝： | LCC-44 |
| 文件頁數(shù)： | 39/204頁 |
| 文件大?。?/td> | 5687K |
| 代理商： | MR83C154XXX-30/883 |
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133
ATtiny40 [DATASHEET]
8263B–AVR–01/2013
17.5.4
TWSA – TWI Slave Address Register
The slave address register contains the TWI slave address used by the slave address match logic to determine if a
master has addressed the slave. When using 7-bit or 10-bit address recognition mode, the high seven bits of the
address register (TWSA[7:1]) represent the slave address. The least significant bit (TWSA0) is used for general
call address recognition. Setting TWSA0 enables general call address recognition logic.
When using 10-bit addressing the address match logic only support hardware address recognition of the first byte
of a 10-bit address. If TWSA[7:1] is set to "0b11110nn", 'nn' will represent bits 9 and 8 of the slave address. The
next byte received is then bits 7 to 0 in the 10-bit address, but this must be handled by software.
When the address match logic detects that a valid address byte has been received, the TWASIF is set and the
TWDIR flag is updated.
If TWPME in TWSCRA is set, the address match logic responds to all addresses transmitted on the TWI bus.
TWSA is not used in this mode.
17.5.5
TWSD – TWI Slave Data Register
The data register is used when transmitting and received data. During transfer, data is shifted from/to the TWSD
register and to/from the bus. Therefore, the data register cannot be accessed during byte transfers. This is pro-
tected in hardware. The data register can only be accessed when the SCL line is held low by the slave, i.e. when
TWCH is set.
When a master reads data from a slave, the data to be sent must be written to the TWSD register. The byte trans-
fer is started when the master starts to clock the data byte from the slave. It is followed by the slave receiving the
acknowledge bit from the master. The TWDIF and the TWCH bits are then set.
When a master writes data to a slave, the TWDIF and the TWCH flags are set when one byte has been received in
the data register. If Smart Mode is enabled, reading the data register will trigger the bus operation, as set by the
TWAA bit in TWSCRB.
Accessing TWSD will clear the slave interrupt flags and the TWCH bit.
17.5.6
TWSAM – TWI Slave Address Mask Register
Bits 7:1 – TWSAM[7:1]: TWI Address Mask
These bits can act as a second address match register, or an address mask register, depending on the TWAE
setting.
If TWAE is set to zero, TWSAM can be loaded with a 7-bit slave address mask. Each bit in TWSAM can mask (dis-
able) the corresponding address bit in the TWSA register. If the mask bit is one the address match between the
incoming address bit and the corresponding bit in TWSA is ignored. In other words, masked bits will always match.
Bit
765
432
10
TWSA[7:0]
TWSA
Read/Write
R/W
Initial Value
000
00
Bit
765
432
10
TWSD[7:0]
TWSD
Read/Write
R/W
Initial Value
000
00
Bit
765
432
10
TWSAM[7:0]
TWAE
TWSAM
Read/Write
R/W
Initial Value
000
00
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