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參數(shù)資料
| 型號(hào)： | MR83C154XXX-30/883 |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 30 MHz, MICROCONTROLLER, CQCC44 |
| 封裝： | LCC-44 |
| 文件頁(yè)數(shù)： | 169/204頁(yè) |
| 文件大小： | 5687K |
| 代理商： | MR83C154XXX-30/883 |
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67
ATtiny40 [DATASHEET]
8263B–AVR–01/2013
The N variable represents the prescale factor (1, 8, 64, 256, or 1024).
As for the Normal mode of operation, the TOV0 Flag is set in the same timer clock cycle that the counter counts
from MAX to 0x00.
11.7.3
Fast PWM Mode
The fast Pulse Width Modulation or fast PWM mode (WGM0[2:0] = 3 or 7) provides a high frequency PWM wave-
form generation option. The fast PWM differs from the other PWM option by its single-slope operation. The counter
counts from BOTTOM to TOP then restarts from BOTTOM. TOP is defined as 0xFF when WGM0[2:0] = 3, and
OCR0A when WGM0[2:0] = 7. In non-inverting Compare Output mode, the Output Compare (OC0x) is cleared on
the Compare Match between TCNT0 and OCR0x, and set at BOTTOM. In inverting Compare Output mode, the
output is set on Compare Match and cleared at BOTTOM. Due to the single-slope operation, the operating fre-
quency of the fast PWM mode can be twice as high as the phase correct PWM mode that use dual-slope
operation. This high frequency makes the fast PWM mode well suited for power regulation, rectification, and DAC
applications. High frequency allows physically small sized external components (coils, capacitors), and therefore
reduces total system cost.
In fast PWM mode, the counter is incremented until the counter value matches the TOP value. The counter is then
cleared at the following timer clock cycle. The timing diagram for the fast PWM mode is shown in Figure 11-6 on
page 67. The TCNT0 value is in the timing diagram shown as a histogram for illustrating the single-slope operation.
The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT0
slopes represent Compare Matches between OCR0x and TCNT0.
Figure 11-6. Fast PWM Mode, Timing Diagram
The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches TOP. If the interrupt is enabled, the
interrupt handler routine can be used for updating the compare value.
In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC0x pins. Setting the
COM0x[1:0] bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by setting
the COM0x[1:0] to three: Setting the COM0A[1:0] bits to one allowes the OC0A pin to toggle on Compare Matches
if the WGM02 bit is set. This option is not available for the OC0B pin (See Table 11-3 on page 72). The actual
OC0x value will only be visible on the port pin if the data direction for the port pin is set as output. The PWM wave-
form is generated by setting (or clearing) the OC0x Register at the Compare Match between OCR0x and TCNT0,
TCNTn
OCRnx Update and
TOVn Interrupt Flag Set
1
Period
2
3
OCnx
(COMnx[1:0] = 2)
(COMnx[1:0] = 3)
OCRnx Interrupt Flag Set
4
5
6
7
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