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參數(shù)資料
| 型號： | MR83C154XXX-30/883 |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 30 MHz, MICROCONTROLLER, CQCC44 |
| 封裝： | LCC-44 |
| 文件頁數(shù)： | 38/204頁 |
| 文件大?。?/td> | 5687K |
| 代理商： | MR83C154XXX-30/883 |
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132
ATtiny40 [DATASHEET]
8263B–AVR–01/2013
Bit 7 – TWDIF: TWI Data Interrupt Flag
This flag is set when a data byte has been successfully received, i.e. no bus errors or collisions have occurred dur-
ing the operation. When this flag is set the slave forces the SCL line low, stretching the TWI clock period. The SCL
line is released by clearing the interrupt flags.
Writing a one to this bit will clear the flag. This flag is also automatically cleared when writing a valid command to
the TWCMDn bits in TWSCRB.
Bit 6 – TWASIF: TWI Address/Stop Interrupt Flag
This flag is set when the slave detects that a valid address has been received, or when a transmit collision has
been detected. When this flag is set the slave forces the SCL line low, stretching the TWI clock period. The SCL
line is released by clearing the interrupt flags.
If TWASIE in TWSCRA is set, a STOP condition on the bus will also set TWASIF. STOP condition will set the flag
only if system clock is faster than the minimum bus free time between STOP and START.
Writing a one to this bit will clear the flag. This flag is also automatically cleared when writing a valid command to
the TWCMDn bits in TWSCRB.
Bit 5 – TWCH: TWI Clock Hold
This bit is set when the slave is holding the SCL line low.
This bit is read-only, and set when TWDIF or TWASIF is set. The bit can be cleared indirectly by clearing the inter-
rupt flags and releasing the SCL line.
Bit 4 – TWRA: TWI Receive Acknowledge
This bit contains the most recently received acknowledge bit from the master.
This bit is read-only. When zero, the most recent acknowledge bit from the maser was ACK and, when one, the
most recent acknowledge bit was NACK.
Bit 3 – TWC: TWI Collision
This bit is set when the slave was not able to transfer a high data bit or a NACK bit. When a collision is detected,
the slave will commence its normal operation, and disable data and acknowledge output. No low values are shifted
out onto the SDA line.
This bit is cleared by writing a one to it. The bit is also cleared automatically when a START or Repeated START
condition is detected.
Bit 2 – TWBE: TWI Bus Error
This bit is set when an illegal bus condition has occured during a transfer. An illegal bus condition occurs if a
Repeated START or STOP condition is detected, and the number of bits from the previous START condition is not
a multiple of nine.
This bit is cleared by writing a one to it.
Bit 1 – TWDIR: TWI Read/Write Direction
This bit indicates the direction bit from the last address packet received from a master. When this bit is one, a mas-
ter read operation is in progress. When the bit is zero a master write operation is in progress.
Bit 0 – TWAS: TWI Address or Stop
This bit indicates why the TWASIF bit was last set. If zero, a stop condition caused TWASIF to be set. If one,
address detection caused TWASIF to be set.
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