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參數(shù)資料
| 型號： | MR83C154XXX-30/883 |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 30 MHz, MICROCONTROLLER, CQCC44 |
| 封裝： | LCC-44 |
| 文件頁數(shù)： | 3/204頁 |
| 文件大?。?/td> | 5687K |
| 代理商： | MR83C154XXX-30/883 |
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100
ATtiny40 [DATASHEET]
8263B–AVR–01/2013
The analog input channel is selected by writing to the MUX bits in ADMUX. Any of the ADC input pins can be
selected as single ended inputs to the ADC.
The ADC generates a 10-bit result which is presented in the ADC Data Registers, ADCH and ADCL. By default,
the result is presented right adjusted, but can optionally be presented left adjusted by setting the ADLAR bit in
ADCSRB.
If the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read ADCH, only. Other-
wise, ADCL must be read first, then ADCH, to ensure that the content of the data registers belongs to the same
conversion. Once ADCL is read, ADC access to data registers is blocked. This means that if ADCL has been read,
and a conversion completes before ADCH is read, neither register is updated and the result from the conversion is
lost. When ADCH is read, ADC access to the ADCH and ADCL Registers is re-enabled.
The ADC has its own interrupt which can be triggered when a conversion completes. When ADC access to the
data registers is prohibited between reading of ADCH and ADCL, the interrupt will trigger even if the result is lost.
15.4
Starting a Conversion
Make sure the ADC is powered by clearing the ADC Power Reduction bit, PRADC, in the Power Reduction Regis-
ter, PRR (see “PRR – Power Reduction Register” on page 27).
A single conversion is started by writing a logical one to the ADC Start Conversion bit, ADSC. This bit stays high as
long as the conversion is in progress and will be cleared by hardware when the conversion is completed. If a differ-
ent data channel is selected while a conversion is in progress, the ADC will finish the current conversion before
performing the channel change.
Alternatively, a conversion can be triggered automatically by various sources. Auto Triggering is enabled by setting
the ADC Auto Trigger Enable bit, ADATE in ADCSRA. The trigger source is selected by setting the ADC Trigger
Select bits, ADTS in ADCSRB (see description of the ADTS bits for a list of the trigger sources). When a positive
edge occurs on the selected trigger signal, the ADC prescaler is reset and a conversion is started. This provides a
method of starting conversions at fixed intervals. If the trigger signal still is set when the conversion completes, a
new conversion will not be started. If another positive edge occurs on the trigger signal during conversion, the edge
will be ignored. Note that an Interrupt Flag will be set even if the specific interrupt is disabled or the Global Interrupt
Enable bit in SREG is cleared. A conversion can thus be triggered without causing an interrupt. However, the Inter-
rupt Flag must be cleared in order to trigger a new conversion at the next interrupt event.
Figure 15-2. ADC Auto Trigger Logic
Using the ADC Interrupt Flag as a trigger source makes the ADC start a new conversion as soon as the ongoing
conversion has finished. The ADC then operates in Free Running mode, constantly sampling and updating the
ADC Data Register. The first conversion must be started by writing a logical one to the ADSC bit in ADCSRA. In
ADSC
ADIF
SOURCE 1
SOURCE n
ADTS[2:0]
CONVERSION
LOGIC
PRESCALER
START
CLK
ADC
.
EDGE
DETECTOR
ADATE
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