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| 型號(hào)： | MR83C154XXX-30/883 |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 30 MHz, MICROCONTROLLER, CQCC44 |
| 封裝： | LCC-44 |
| 文件頁(yè)數(shù)： | 186/204頁(yè) |
| 文件大?。?/td> | 5687K |
| 代理商： | MR83C154XXX-30/883 |
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82
ATtiny40 [DATASHEET]
8263B–AVR–01/2013
OCR1A. The OCR1A defines the top value for the counter, hence also its resolution. This mode allows greater con-
trol of the Compare Match output frequency. It also simplifies the operation of counting external events.
The timing diagram for the CTC mode is shown in Figure 12-4. The counter value (TCNT1) increases until a Com-
pare Match occurs between TCNT1 and OCR1A, and then counter (TCNT1) is cleared.
Figure 12-4. CTC Mode, Timing Diagram
An interrupt can be generated each time the counter value reaches the TOP value by using the OCF1A Flag. If the
interrupt is enabled, the interrupt handler routine can be used for updating the TOP value. However, changing TOP
to a value close to BOTTOM when the counter is running with none or a low prescaler value must be done with
care since the CTC mode does not have the double buffering feature. If the new value written to OCR1A is lower
than the current value of TCNT1, the counter will miss the Compare Match. The counter will then have to count to
its maximum value (0xFF) and wrap around starting at 0x00 before the Compare Match can occur. As for the Nor-
mal mode of operation, the TOV1 Flag is set in the same timer clock cycle that the counter counts from MAX to
0x00.
12.7.3
Normal, 16-bit Mode
In 16-bit mode, see Table 12-3 on page 81, the counter (TCNT1H/L) is a incrementing until it overruns when it
passes its maximum 16-bit value (MAX = 0xFFFF) and then restarts from the bottom (0x0000). The Overflow Flag
(TOV1) will be set in the same timer clock cycle as the TCNT1H/L becomes zero. The TOV1 Flag in this case
behaves like a 17th bit, except that it is only set, not cleared. However, combined with the timer overflow interrupt
that automatically clears the TOV1 Flag, the timer resolution can be increased by software. There are no special
cases to consider in the Normal mode, a new counter value can be written anytime. The Output Compare Unit can
be used to generate interrupts at some given time.
12.7.4
8-bit Input Capture Mode
The Timer/Counter1 can also be used in an 8-bit Input Capture mode, see Table 12-3 on page 81 for bit settings.
For full description, see the section “Input Capture Unit” on page 79.
12.7.5
16-bit Input Capture Mode
The Timer/Counter1 can also be used in a 16-bit Input Capture mode, see Table 12-3 on page 81 for bit settings.
For full description, see the section “Input Capture Unit” on page 79.
12.8
Timer/Counter Timing Diagrams
The Timer/Counter is a synchronous design and the timer clock (clk
T1) is therefore shown as a clock enable signal
in the following figures. The figures include information on when Interrupt Flags are set. Figure 12-5 contains timing
data for basic Timer/Counter operation. The figure shows the count sequence close to the MAX value.
TCNTn
OCnA
(Toggle)
OCnx Interrupt Flag Set
1
4
Period
2
3
(COMnA[1:0] = 1)
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