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參數(shù)資料
| 型號(hào)： | MR83C154XXX-30/883 |
| 廠商： | ATMEL CORP |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 30 MHz, MICROCONTROLLER, CQCC44 |
| 封裝： | LCC-44 |
| 文件頁(yè)數(shù)： | 171/204頁(yè) |
| 文件大?。?/td> | 5687K |
| 代理商： | MR83C154XXX-30/883 |
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69
ATtiny40 [DATASHEET]
8263B–AVR–01/2013
In phase correct PWM mode the counter is incremented until the counter value matches TOP. When the counter
reaches TOP, it changes the count direction. The TCNT0 value will be equal to TOP for one timer clock cycle. The
timing diagram for the phase correct PWM mode is shown on Figure 11-7. The TCNT0 value is in the timing dia-
gram shown as a histogram for illustrating the dual-slope operation. The diagram includes non-inverted and
inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes represent Compare Matches
between OCR0x and TCNT0.
The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches BOTTOM. The Interrupt Flag can
be used to generate an interrupt each time the counter reaches the BOTTOM value.
In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the OC0x pins. Setting
the COM0x[1:0] bits to two will produce a non-inverted PWM. An inverted PWM output can be generated by setting
the COM0x[1:0] to three: Setting the COM0A0 bits to one allows the OC0A pin to toggle on Compare Matches if
the WGM02 bit is set. This option is not available for the OC0B pin (See Table 11-4 on page 72). The actual OC0x
value will only be visible on the port pin if the data direction for the port pin is set as output. The PWM waveform is
generated by clearing (or setting) the OC0x Register at the Compare Match between OCR0x and TCNT0 when the
counter increments, and setting (or clearing) the OC0x Register at Compare Match between OCR0x and TCNT0
when the counter decrements. The PWM frequency for the output when using phase correct PWM can be calcu-
lated by the following equation:
The N variable represents the prescale factor (1, 8, 64, 256, or 1024).
The extreme values for the OCR0x Register represent special cases when generating a PWM waveform output in
the phase correct PWM mode. If the OCR0x is set equal to BOTTOM, the output will be continuously low and if set
equal to TOP the output will be continuously high for non-inverted PWM mode. For inverted PWM the output will
have the opposite logic values.
At the very start of period 2 in Figure 11-7 on page 68 OCnx has a transition from high to low even though there is
no Compare Match. The point of this transition is to guarantee symmetry around BOTTOM. There are two cases
that give a transition without Compare Match.
OCR0x changes its value from TOP, like in Figure 11-7 on page 68. When the OCR0x value is TOPthe OCnx
pin value is the same as the result of a down-counting Compare Match. To ensure symmetry around BOTTOM
the OCnx value at TOP must correspond to the result of an up-counting Compare Match.
The timer starts counting from a value higher than the one in OCR0x, and for that reason misses the Compare
Match and hence the OCnx change that would have happened on the way up.
11.8
Timer/Counter Timing Diagrams
The Timer/Counter is a synchronous design and the timer clock (clk
T0) is therefore shown as a clock enable signal
in the following figures. The figures include information on when Interrupt Flags are set. Figure 11-8 on page 70
contains timing data for basic Timer/Counter operation. The figure shows the count sequence close to the MAX
value in all modes other than phase correct PWM mode.
fOCnxPCPWM
f
clk_I/O
2
N
TOP
--------------------------------
=
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