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參數(shù)資料
| 型號(hào)： | MR83C154XXX-30/883 |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 30 MHz, MICROCONTROLLER, CQCC44 |
| 封裝： | LCC-44 |
| 文件頁(yè)數(shù)： | 138/204頁(yè) |
| 文件大?。?/td> | 5687K |
| 代理商： | MR83C154XXX-30/883 |
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39
ATtiny40 [DATASHEET]
8263B–AVR–01/2013
Bits 7:6 – ISC0[1:0]: Interrupt Sense Control
The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corresponding interrupt
mask are set. The level and edges on the external INT0 pin that activate the interrupt are defined in Table 9-2. The
value on the INT0 pin is sampled before detecting edges. If edge or toggle interrupt is selected, pulses that last lon-
ger than one clock period will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If
low level interrupt is selected, the low level must be held until the completion of the currently executing instruction
to generate an interrupt.
9.3.2
GIMSK – General Interrupt Mask Register
Bit 7 – Res: Reserved Bit
This bit is reserved and will always read as zero.
Bit 6 – PCIE2: Pin Change Interrupt Enable 2
When the PCIE1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin change interrupt 2 is
enabled. Any change on any enabled PCINT[17:12] pin will cause an interrupt. The corresponding interrupt of Pin
Change Interrupt Request is executed from the PCI0 Interrupt Vector. PCINT[17:12] pins are enabled individually
by the PCMSK2 Register.
Bit 5 – PCIE1: Pin Change Interrupt Enable 1
When the PCIE1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin change interrupt 1 is
enabled. Any change on any enabled PCINT[11:8] pin will cause an interrupt. The corresponding interrupt of Pin
Change Interrupt Request is executed from the PCI1 Interrupt Vector. PCINT[11:8] pins are enabled individually by
the PCMSK1 Register.
Bit 4 – PCIE0: Pin Change Interrupt Enable 0
When the PCIE0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin change interrupt 0 is
enabled. Any change on any enabled PCINT[7:0] pin will cause an interrupt. The corresponding interrupt of Pin
Change Interrupt Request is executed from the PCI0 Interrupt Vector. PCINT[7:0] pins are enabled individually by
the PCMSK0 Register.
Bits 3:1 – Res: Reserved Bits
These bits are reserved and will always read as zero.
Initial Value
0
Table 9-2.
Interrupt 0 Sense Control
ISC01
ISC00
Description
0
The low level of INT0 generates an interrupt request.
0
1
Any logical change on INT0 generates an interrupt request.
1
0
The falling edge of INT0 generates an interrupt request.
1
The rising edge of INT0 generates an interrupt request.
Bit
7
65
43
2
1
0
–
PCIE2
PCIE1
PCIE0
–
INT0
GIMSK
Read/Write
R
R/W
R
R/W
Initial Value
0
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